• JSTS:Journal of Semiconductor Technology and Science
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• 제15권1호
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• pp.41-47
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• 2015

In this paper, the effective electron Schottky barrier height (${\Phi}_{Bn}$) of the Ni silicide/n-silicon (100) interface was studied in accordance with different thicknesses of the antimony (Sb) interlayer for high performance n-channel MOSFETs. The Sb interlayers, varying its thickness from 2 nm to 10 nm, were deposited by radio frequency (RF) sputtering on lightly doped n-type Si (100), followed by the in situ deposition of Ni/TiN (15/10 nm). It is found that the sample with a thicker Sb interlayer shows stronger ohmic characteristics than the control sample without the Sb interlayer. These results show that the effective ${\Phi}_{Bn}$ is considerably lowered by the influence of the Sb interlayer. However, the current level difference between Schottky diodes fabricated with Sb/Ni/TiN (8/15/10 nm) and Sb/Ni/TiN (10/15/10 nm) structures is almost same. Therefore, considering the process time and cost, it can be said that the optimal thickness of the Sb interlayer is 8 nm. The effective ${\Phi}_{Bn}$ of 0.076 eV was achieved for the Schottky diode with Sb/Ni/TiN (8/15/10 nm) structure. Therefore, this technology is suitable for high performance n-channel MOSFETs.

• 한국정보통신학회논문지
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• 제15권9호
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• pp.2000-2006
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• 2011

본 연구에서는 이중게이트(Double Gate; DG) MOSFET의 채널내 도핑분포 형태에 따른 드레인유기장벽감소(drain induced barrier lowering; DIBL) 현상을 분석하였다. DGMOSFET는 기존 MOSFET에서 발생하는 단채널효과를 감소시킬 수 있다는 장점 때문에 많은 연구가 진행 중에 있다. DIBL은 높은 드레인 전압에 의하여 발생하는 에너지밴드의 변화가 문턱전압의 감소로 니타나는 단채널효과이다. 이러한 DIBL을 DGMOSFET의 구조적 파라미터 및 채널 내 도핑분포함수의 변화에 따라 분석하고자 한다. 이를 위하여 가우시안 분포함수를 이용하여 포아송방정식의 해석학적 모델을 유도하였다. 본 논문에서 사용한 해석학적 포아송방정식의 전위분포모델 및 DIBL 모델의 타당성을 입증하기 위하여 수치해석학적 결과값과 비교하였으며 이 모델을 이용하여 DGMOSFET의 DIBL을 분석하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권4호
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• pp.367-380
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• 2013

In this paper, an analytical threshold voltage model is developed for a short-channel double-material-gate (DMG) strained-silicon (s-Si) on silicon-germanium ($Si_{1-X}Ge_X$) MOSFET structure. The proposed threshold voltage model is based on the so called virtual-cathode potential formulation. The virtual-cathode potential is taken as minimum channel potential along the transverse direction of the channel and is derived from two-dimensional (2D) potential distribution of channel region. The 2D channel potential is formulated by solving the 2D Poisson's equation with suitable boundary conditions in both the strained-Si layer and relaxed $Si_{1-X}Ge_X$ layer. The effects of a number of device parameters like the Ge mole fraction, Si film thickness and gate-length ratio have been considered on threshold voltage. Further, the drain induced barrier lowering (DIBL) has also been analyzed for gate-length ratio and amount of strain variations. The validity of the present 2D analytical model is verified with ATLAS$^{TM}$, a 2D device simulator from Silvaco Inc.

• Transactions on Electrical and Electronic Materials
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• 제17권5호
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• pp.270-274
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• 2016

This article investigates the use of the Gaussian-channel doping profile for the control of the short-channel effects in the double-gate MOSFET whereby a two-dimensional (2D) quantum simulation was used. The simulations were completed through a self-consistent solving of the 2D Poisson equation and the Schrodinger equation within the non-equilibrium Green’s function (NEGF) formalism. The impacts of the p-type-channel Gaussian-doping profile parameters such as the peak doping concentration and the straggle parameter were studied in terms of the drain current, on-current, off-current, sub-threshold swing (SS), and drain-induced barrier lowering (DIBL). The simulation results show that the short-channel effects were improved in correspondence with incremental changes of the straggle parameter and the peak doping concentration.

• Journal of Advanced Marine Engineering and Technology
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• 제40권1호
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• pp.69-74
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• 2016

낙동강 하구를 둘러싸고 있는 울타리 섬들 중 하나인 진우도 남측 해역에서의 해저지형 변동을 2006년 6월부터 2015년 4월까지 총 16회의 수심측정 자료를 이용하여 연구하였다. 이 해역의 동쪽은 진우도와 신자도 사이로 서낙동강과 낙동강 하구둑에서 유입되는 담수의 이동 통로로 해수와 담수의 유입 및 유출 수로가 위치해 있으며, 서쪽은 눌차도와 진우도 사이로 부산신항의 연결잔교를 통하여 해수가 이동하는 수로가 존재한다. 동쪽 수로 연장에서의 변화가 이 해역의 해저지형 변화를 주도한다. 지형 변동은 퇴적 또는 침식만이 일방적으로 진행되는 것이 아니라 퇴적 또는 침식이 진행되다가 어느 일정한 단계가 지나면 급격한 변형을 통하여 회귀하는 형태를 보이고 있다. 특히 연구 지역의 총 퇴적량은 2006년 6월부터 2013년 3월까지 증가하다가 2013년 10월 자료부터 급격히 감소하여 2015년 4월까지 큰 변동없이 유지되고 있는 것을 보여주고 있다는 결론을 얻었다. 이것은 2013년 10월 초에 한반도에 영향을 준 제 24호 태풍 '다나스' (Danas)에 의해 진우도 남측해역의 토사가 외해로 쓸려나간 현상으로 판단된다. 진우도 동쪽에 위치한 수로의 변동은 동서, 남북 방향의 측선을 이용하여 분석하였는데, 수로의 최대수심 위치가 2006년 6월에 비해 2015년 4월까지 서쪽으로 약 100 ~ 130 m, 북쪽으로 약 200 m 이동한 것으로 확인되었다.

• 대한기계학회논문집A
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• 제28권1호
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• pp.63-69
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• 2004

It is of great interest to enhance mixing performance in a microchannel in which the flow is usually characterized as a low Reynolds number (Re) so that good mixing is quite difficult to be achieved in this laminar flow regime. In this regard, we present a new chaotic passive micromixer, named Barrier Embedded Micromixer (BEM), of which the mixing mechanism is based on chaotic flows. In BEM, chaotic flow is induced by periodic perturbation of the velocity field due to periodically inserted barriers along the channel wall while a helical type of flow is obtained by slanted grooves on the bottom surface of the channel in the pressure driven flow. To experimentally compare the mixing performance, a T-microchannel and a microchannel with only slanted grooves were also fabricated. All microchannels were made of PDMS (Polydimethylsiloxane) from SU-8 masters that were fabricated by conventional photolithography. Mixing performance was experimentally characterized with respect to an average mixing intensity by means of color change of phenolphthalein as pH indicator. It was found that mixing efficiency decreases as Re increases for all three micromixers. Experimental results obviously indicate that BEM has better mixing performance than the other two. Chaotic mixing mechanism, suggested in this study, can be easily applied to integrated microfluidic systems , such as Micro-Total-Analysis-System, Lab-on-a-chip and so on.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.342-343
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• 2012

We studied the Drain-Induced-Barrier-Lowering (DIBL) effect by different drain engineering. One other drain engineering is symmetric source-drain n-channel MOSFETs (SSD NMOSs), the other drain engineering is asymmetric source-drain n-channel MOSFETs (ASD NMOSs). Devices were fabricated using state of art 40 nm dynamic-random-access-memory (DRAM) technology. These devices have different modes which are deep drain junction mode in SSD NMOSs and shallow drain junction mode in ASD NMOSs. The shallow drain junction mode means that drain is only Lightly-Doped-Drain (LDD). The deep drain junction mode means that drain have same process with source. The threshold voltage gap between low drain voltage ($V_D$=0.05V) and high drain voltage ($V_D$=3V) is 0.088V in shallow drain junction mode and 0.615V in deep drain junction mode at $0.16{\mu}m$ of gate length. The DIBL coefficients are 26.5 mV/V in shallow drain junction mode and 205.7 mV/V in deep drain junction mode. These experimental results present that DIBL effect is higher in deep drain junction mode than shallow drain junction mode. These results are caused that ASD NMOSs have low drain doping level and low lateral electric field.

• Journal of information and communication convergence engineering
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• 제9권6호
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• pp.738-742
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• 2011

This paper has studied drain induced barrier lowering(DIBL) for Double Gate MOSFET(DGMOSFET) using analytical potential model. Two dimensional analytical potential model has been presented for symmetrical DGMOSFETs with process parameters. DIBL is very important short channel effects(SCEs) for nano structures since drain voltage has influenced on source potential distribution due to reduction of channel length. DIBL has to be small with decrease of channel length, but it increases with decrease of channel length due to SCEs. This potential model is used to obtain the change of DIBL for DGMOSFET correlated to channel doping profiles. Also device parameters including channel length, channel thickness, gate oxide thickness and doping intensity have been used to analyze DIBL.

• 한국전기전자재료학회논문지
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• 제23권10호
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• pp.763-766
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• 2010

By improving the conducting process of metal source/drain (S/D) in direct contact with the channel, schottky barrier metal-oxide-semiconductor field effect transistors (SB MOSFETs) reveal low extrinsic parasitic resistances, offer easy processing and allow for well-defined device geometries down to the smallest dimensions. In this work, we investigated the arrhenius plots of the SB MOSFETs with different S/D schottky barrier (SB) heights between simulated and experimental current-voltage characteristics. We fabricated SB MOSFETs using difference S/D metals such as Cr (${\Phi}_{Cr}$ ~4.5 eV) and Ni (${\Phi}_{Ni}$~5.2 eV), respectively. Schottky barrier height (${\Phi}_B$) of the fabricated devices were measured to be 0.25~0.31 eV (Cr-S/D device) and 0.16~0.18 eV (Ni-S/D device), respectively in the temperature range of 300 K and 475 K. The experimental results have been compared with 2-dimensional simulations, which allowed bandgap diagram analysis.

• JSTS:Journal of Semiconductor Technology and Science
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• 제5권2호
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• pp.69-76
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• 2005

Interface-trap density, lifetime and Schottky barrier height of erbium-silicided Schottky diode are evaluated using equivalent circuit method. The extracted interface trap density, lifetime and Schottky barrier height for hole are determined as $1.5{\times}10^{13} traps/cm^2$, 3.75 ms and 0.76 eV, respectively. The interface traps are efficiently cured by $N_2$ annealing. Based on the diode characteristics, various sizes of erbium- silicided/platinum-silicided n/p-type Schottky barrier metal-oxide-semiconductor field effect transistors (SB-MOSFETs) are manufactured from 20 m to 35nm. The manufactured SB-MOSFETs show excellent drain induced barrier lowering (DIBL) characteristics due to the existence of Schottky barrier between source and channel. DIBL and subthreshold swing characteristics are compatible with the ultimate scaling limit of double gate MOSFETs which shows the possible application of SB-MOSFETs in nanoscale regime.