• Journal of the Korean Institute of Telematics and Electronics
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• v.16 no.2
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• pp.7-14
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• 1979

Design considerations of I2L are discussed with particular emphasis on the upward current gain of the npn transistor, 6J Several test structures have been fabricated to measure the DC and AC characteristics of the I2L basic cell and the base current components of the npn transistor. A T flip-flop has also been designed and fabricated using the I2L technology. The upward current gain of 10 the speed -power product of the 2.6pJ/gate and the minimum propagation delay time of 36 nsec have been obtained from the test structure. The maxmum toggle frequency of the T flip -flop has been measured to be 3.5 MHz.

• The Magazine of the IEIE
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• v.24 no.6
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• pp.38-49
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• 1997

0.4mm Resign Rule의 Super Low Power Dissipation, Low Voltage. Operation-5- Full CMOS SRAM Cell을 개발하였다. Retrograde Well과 PSL(Poly Spacer LOCOS) Isolation 공정을 사용하여 1.76mm의 n+/p+ Isolation을 구현하였으며 Ti/TiN Local Interconnection을 사용하여 Polycide수준의 Rs와 작은 Contact저항을 확보하였다. p-well내의 Boron이 Field oxide에 침적되어 n+/n-well Isolation이 취약해짐을 Simulation을 통해 확인할 수 있었으며, 기생 Lateral NPN Bipolar Transistor의 Latch Up 특성이 취약해 지는 n+/n-wellslze는 0.57mm이고, 기생 Vertical PNP Bipolar Transistor는 p+/p-well size 0.52mm까지 안정적인 Current Gain을 유지함을 알 수 있었다. Ti/TiN Local Interconnection의 Rs를 Polycide 수준으로 낮추는 것은 TiN deco시 Power를 증가시키고 Pressure를 감소시킴으로써 실현할 수 있었다. Static Noise Margin분석을 통해 Vcc 0.6V에서도 Cell의 동작 Margin이 있음을 확인할 수 있었으며, Load Device의 큰 전류로 Soft Error를 개선할수 있었다. 본 공정으로 제조한 1M Full CMOS SRAM에서 Low Vcc margin 1.0V, Stand-by current 1mA이하(Vcc=3.7V, 85℃기준) 를 얻을 수 있었다.

• Transactions on Electrical and Electronic Materials
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• v.5 no.1
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• pp.7-10
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• 2004

A new method for fabrication of transistor like structure of the bifacial solar cell using spin-on doping and electroless plating has been proposed and the basic characteristics of the bifacial cell have been investigated. It is found that 9％ increase in short circuit current is achieved with bifacial connection than the unifacial connection. Some unwanted effect of the series resistance on collection efficiency under different mode of illumination has been pointed out. Loss mechanisms inherent in the transistor like bifacial structure have also been discussed.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.234-241
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• 2012

This paper proposes a novel design methodology considering transistor layout variation. The proposed design technique is to improve the transistor's electrical characteristics without performing a circuit simulation to extract transistor layout variation. There are three advantages in the proposed method. Firstly, there is no need to change the normal design flow used in layout designs. Secondly, there is no need to perform simulation in order to extract the transistor layout variation. Thirdly, early warnings in layout design lead to decreasing the number of post layout simulations. Less post layout simulations will decrease the number of iterations in the design cycle and shorten design period. The number of bad transistors in the early design phase were reduced from 17.8% to 2.9% by applying eDRC environment for layout designers to develop Standard Cell Library.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.8
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• pp.1227-1234
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• 2013

An analog array with a 1.2 double poly floating gate transistor has been developed with a standard CMOS fabrication process. The programming of each cell by means of an efficient control circuit eliminates the unnecessary erasing operation which has been widely used in conventional analog memories. It is seen that the path of the signal for both the programming and the reading is almost exactly the same since just one comparator supports both operations. It helps to eliminate the effects of the amplifier input-offset voltage problem on the output voltage for the read operation. In the array, there is no pass transistor isolating a cell of interest from the adjacent cells in the array. Instead of the extra transistors, one extra bias voltage, Vmid, is employed. The experimental results from the memory shows that the resolution of the memory is equivalent to the information content of at least six digital cells. Programming/erasing of each cell is achieved with no detectable disturbance of adjacent cells. Finally, the unique shape of the injector structure in a EEPROM is adopted as a cell of analog array. It reduces the programming voltage below the transistor breakdown voltage without any special fabrication process.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.10
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• pp.30-37
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• 1998

An analog array with a 1.2 $\mu\textrm{m}$ double poly floating gate transistor has been developed with a standard CMOS fabrication process. The programming of each cell by means of an efficient control circuit eliminates the unnecessary erasing operation which has been widely used in conventional analog memories. It is seen that the path of the signal for both the programming and the reading is almost exactly the same since just one comparator supports both operations. It helps to eliminate the effects of the amplifier input-offset voltage problem on the output voltage for the read operation. In the array, there is no pass transistor isolating a cell of interest from the adjacent cells in the array. Instead of the extra transistors, one extra bias voltage, Vmid, is employed. The experimental results from the memory shows that the resolution of the memory is equivalent to the information content of at least six digital cells. Programming/erasing of each cell is achieved with no detectable disturbance of adjacent cells. Finally, the unique shape of the injector structure in a EEPROM is adopted as a cell of analog array. It reduces the programming voltage below the transistor breakdown voltage without any special fabrication process.

• Proceedings of the Korea Society for Industrial Systems Conference
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• 2002.06a
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• pp.195-199
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• 2002

This paper describes the effect of substrate back bias of CMOS Inverter. When the substrate back bias applied in body, the MOS transistor threshold voltage increased and drain saturation current decreased. The back gate reverse bias or substrate bias has been widely utilized and the following advantage has suppressing subthreshold leakage, lowering parasitic junction capacitance, preventing latch up or parasitic bipolar transistor, etc. When the reverse voltage applied substrate, this paper stimulated the propagation delay time CMOS inverter.

• 전기의세계
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• v.38 no.4
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• pp.12-19
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• 1989

16Mb DRAM을 개발하는데 필요한 주요한 기술적인 문제점으로 설계면에서는 전력소모, Noise, Vcc내부 전압강하회로를 들 수 있다. 기술적인 면은 CELL을 어떻게 형상화느냐에 따라 문제가 다르게 나타나나 단차에 따른 photo/etching, 박막의 leakage전류와 reliability, short channel에 따른 transistor특성의 안정화등이 있다. 특히 16Mb에서는 stack형, stack과 trench의 병합형이 cell의 주요형태가 될 전망이다.

• ETRI Journal
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• v.35 no.4
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• pp.594-602
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• 2013

This paper proposes printed organic one-time programmable read-only memory (PROM). The organic PROM cell consists of a capacitor and an organic p-type metal-oxide semiconductor (PMOS) transistor. Initially, all organic PROM cells with unbroken capacitors store "0." Some organic PROM cells are programmed to "1" by electrically breaking each capacitor with a high voltage. After the capacitor breaking, the current flowing through the PROM cell significantly increases. The memory data is read out by sensing the current in the PROM cell. 16-bit organic PROM cell arrays are fabricated with the printed organic PMOS transistor and capacitor process. The organic PROM cells are programmed with -50 V, and they are read out with -20 V. The area of the 16-bit organic PROM array is 70.6 $mm^2$.

• Journal of Power Electronics
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• v.17 no.2
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• pp.561-569
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• 2017

Power converter design requires simulation accuracy. In addition to the requirement of accurate models of power semiconductor devices, this paper highlights the role of considering a very good description of the converter circuit layout for an accurate simulation of its electrical behavior. This paper considers a simple experimental circuit including one switching cell where a MOSFET transistor controls the diode under test. The turn-off transients of the diode are captured, over which the circuit wiring has a major influence. This paper investigates the necessity for accurate modeling of the experimental test circuit wiring and the MOSFET transistor. It shows that a simple wiring inductance as the circuit wiring representation is insufficient. An adequate model and identification of the model parameters are then discussed. Results are validated through experimental and simulation results.