• ETRI Journal
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• 제26권6호
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• pp.575-582
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• 2004

Fully-depleted silicon-on-insulator (FD-SOI) devices with a 15 nm SOI layer thickness and 60 nm gate lengths for analog applications have been investigated. The Si selective epitaxial growth (SEG) process was well optimized. Both the single- raised (SR) and double-raised (DR) source/drain (S/D) processes have been studied to reduce parasitic series resistance and improve device performance. For the DR S/D process, the saturation currents of both NMOS and PMOS are improved by 8 and 18%, respectively, compared with the SR S/D process. The self-heating effect is evaluated for both body contact and body floating SOI devices. The body contact transistor shows a reduced self-heating ratio, compared with the body floating transistor. The static noise margin of an SOI device with a $1.1\;{\mu}m^2$ 6T-SRAM cell is 190 mV, and the ring oscillator speed is improved by 25 % compared with bulk devices. The DR S/D process shows a higher open loop voltage gain than the SR S/D process. A 15 nm ultra-thin body (UTB) SOI device with a DR S/D process shows the same level of noise characteristics at both the body contact and body floating transistors. Also, we observed that noise characteristics of a 15 nm UTB SOI device are comparable to those of bulk Si devices.

• 전자공학회논문지SC
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• 제37권2호
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• pp.43-49
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• 2000

본 논문에서는 저전압 저전력 시스템에 응용 가능한 CMOS 4상한 아날로그 멀티플라이어를 제안하였다. 제안된 멀티플라이어는 저전압에서 동작이 용이하며 아날로그 회로를 설계하는데 자주 이용되는 LV(Low-Voltage) 상보형 트랜지스터 방식의 특성을 이용하였다. LV 상보형 구조는 등가 문턱전압을 감소시킴으로서 회로의 동작전압을 감소시킬 수 있는 특징이 있다. 설계된 회로의 특성은 2V 공급전압하에서 0.6㎛ CMOS 공정파라미터를 갖는 HSPICE 시뮬레이션을 통하여 측정되었다. 이때 ±0.5V까지의 입력선형 범위내에서 선형성에 대한 오차는 1%미만이었다. 또한 -3㏈ 점에서의 대역폭은 290㎒, 그리고 전력소모는 373㎼값을 나타내었다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.549-549
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• 2012

Early detection of cancer biomarkers in the blood is of vital importance for reducing the mortality and morbidity in a number of cancers. From this point of view, immunosensors based on nanowire (NW) and carbon nanotube (CNT) field-effect transistors (FETs) that allow the ultra-sensitive, highly specific, and label-free electrical detection of biomarkers received much attention. Nevertheless 1D nano-FET biosensors showed high performance, several challenges remain to be resolved for the uncomplicated, reproducible, low-cost and high-throughput nanofabrication. Recently, two-dimensional (2D) graphene and reduced GO (RGO) nanosheets or films find widespread applications such as clean energy storage and conversion devices, optical detector, field-effect transistors, electromechanical resonators, and chemical & biological sensors. In particular, the graphene- and RGO-FETs devices are very promising for sensing applications because of advantages including large detection area, low noise level in solution, ease of fabrication, and the high sensitivity to ions and biomolecules comparable to 1D nano-FETs. Even though a limited number of biosensor applications including chemical vapor deposition (CVD) grown graphene film for DNA detection, single-layer graphene for protein detection and single-layer graphene or solution-processed RGO film for cell monitoring have been reported, development of facile fabrication methods and full understanding of sensing mechanism are still lacking. Furthermore, there have been no reports on demonstration of ultrasensitive electrical detection of a cancer biomarker using the graphene- or RGO-FET. Here we describe scalable and facile fabrication of reduced graphene oxide FET (RGO-FET) with the capability of label-free, ultrasensitive electrical detection of a cancer biomarker, prostate specific antigen/${\alpha}$ 1-antichymotrypsin (PSA-ACT) complex, in which the ultrathin RGO channel was formed by a uniform self-assembly of two-dimensional RGO nanosheets, and also we will discuss about the immunosensing mechanism.

• 대한전자공학회논문지SD
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• 제44권7호통권361호
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• pp.37-44
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• 2007

GSM 셀룰러폰을 위한 저전압 고선형 바이폴라 OTA와 이룡 이용한 IF bandpass filter(BPF)를 제안하였다. OTA는 저전압 선형 transconductor, translinear 전류이득 셀, 그리고 3개의 전류 미러로 구성 되어있다. BPF는 2개의 동일한 2차 BPF를 직렬 연결한 형태인데, 2차 BPF는 저항과 커패시터 그리고 2개의 OTA와 커패시터로 된 ground simulated inductor로 구성되어 있다. 8GHz bipolar transistor-array를 사용한 SPICE 시뮬레이션에서는 1mS의 transconductance의 OTA가 ${\pm}2%$ 이하의 선형 오차와 ${\pm}2\;V$에서 ${\pm}0.65\;V$이상의 선형범위를 가짐을 보여준다. transconductor의 온도계수는 $-90ppm/^{\circ}C$이하이다. BPF는 중심 주파수는 $85MHz\;Q$값은 80이 되도록 설계하였다. 중심주파수에서의 온도계수는 $-182ppm/^{\circ}C$이고, BPF의 소비전력은 128mW 이다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -1
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• pp.658-661
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• 2002

An analog multiplier-divider circuit that realized through the use of OTAs, which does not require external passive circuit elements and temperature compensated, is proposed in this paper. Since the scheme is realized in such a way that employs only OTA as a standard cell, the circuit is simple and can be easily constructed from commercially available IC. The circuit bandwidth is wide and close to the transistor f$\sub$T/. Simulation results that demonstrate the performances of the multiplier-divider circuit are included.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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• pp.473-476
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• 2004

AS supply voltage of DRAM is scaled down, voltage circuit that is stable from external noise is more important. $V_{PP}$ voltage is very important, it is biased to gate of memory cell transistor and possible to read and write without voltage down. It has both high pump gain and high power efficiency therefore charge pump circuit is proposed. The circuit is simulated by 0.18${\mu}m$ memory process and 1.2V supply voltage. Compare to CCTS, it is improved 0.43V of pump gain, $3.06\%$ of power efficiency at 6 stage.

• 한국공작기계학회:학술대회논문집
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• 한국공작기계학회 2004년도 춘계학술대회 논문집
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• pp.269-274
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• 2004

As next generation display, TFT LCD gets into the spotlight, and the bigger glass size is required. Currently, its display size is 1500 mm by 1870 mm at the six generation comparing with 300mm by 400 mm at the first one and the size is increasing continuously, which cause the difficulties to apply the cleaning operation including the general brush cleaning. In this study, water-jet cleaning operation has been introduced, which spent the less water them other cleaning methods. Throughout the experiment, is has been found the possible damage of the declined cell and the variation of the tilt bias angle depending upon the increasing time. In addition, the simulation predicts the glass bending of the display.

• ETRI Journal
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• 제34권1호
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• pp.134-137
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• 2012

Power metal-oxide semiconductor field-effect transistor (MOSFET) devices are widely used in power electronics applications, such as brushless direct current motors and power modules. For a conventional power MOSFET device such as trench double-diffused MOSFET (TDMOS), there is a tradeoff relationship between specific on-state resistance and breakdown voltage. To overcome the tradeoff relationship, a super-junction (SJ) trench MOSFET (TMOSFET) structure is studied and designed in this letter. The processing conditions are proposed, and studies on the unit cell are performed for optimal design. The structure modeling and the characteristic analyses for doping density, potential distribution, electric field, width, and depth of trench in an SJ TMOSFET are performed and simulated by using of the SILVACO TCAD 2D device simulator, Atlas. As a result, the specific on-state resistance of 1.2 $m{\Omega}-cm^2$ at the class of 100 V and 100 A is successfully optimized in the SJ TMOSFET, which has the better performance than TDMOS in design parameters.

• Journal of Information Display
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• 제7권1호
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• pp.35-40
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• 2006

Organic light-emitting diode (OLED) display panel using the charge-pump (CP) pixel addressing scheme was fabricated, and the results show that it is applicable for information display. A CP-OLED panel with 64 ${\times}$ 64 pixels consisting of thin-film capacitors and amorphous silicon Schottky diodes was fabricated using conventional thin-film processes. The pixel drive circuit passes electrical current into the OLED cell during most of the frame period as in the thin-film transistor (TFT)-based active-matrix (AM) OLED displays. In this study, the panel was operated at a voltage level of below 4 V, and this operation voltage can be reduced by eliminating the overlap capacitance between the column bus line and the common electrode.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.346-346
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• 2010

A capacitorless one transistor dynamic random access memory (1T-DRAM) on silicon-germanium-on-insulator substrate was investigated. SGOI technology can make high effective mobility because of lattice mismatch between the Si channel and the SiGe buffer layer. To evaluate memory characteristics of 1T-DRAM, the floating body effect is generated by impact ionization (II) and gate induced drain leakage (GIDL) current. Compared with use of impact ionization current, the use of GIDL current leads to low power consumption and larger sense margin.