• Journal of the Semiconductor & Display Technology
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• v.6 no.3
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• pp.19-23
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• 2007

The NiSi is very promising candidate for the metallization in 45 nm CMOS process such as FUSI(fully silicided) gate and source/drain contact because it exhibits non-size dependent resistance, low silicon consumption and mid-gap workfunction. Ni film was first deposited by using ALD (atomic layer deposition) technique with Bis-Ni precursor and $H_2$ reactant gas at $220^{\circ}C$ with deposition rate of $1.25\;{\AA}/cycle$. The as-deposited Ni film exhibited a sheet resistance of $5\;{\Omega}/{\square}$. RTP (repaid thermal process) was then performed by varying temperature from $400^{\circ}C$ to $900^{\circ}C$ in $N_2$ ambient for the formation of NiSi. The process temperature window for the formation of low-resistance NiSi was estimated from $600^{\circ}C$ to $800^{\circ}C$ and from $700^{\circ}C$ to $800^{\circ}C$ with and without Ti capping layer. The respective sheet resistance of the films was changed to $2.5\;{\Omega}/{\square}$ and $3\;{\Omega}/{\square}$ after silicidation. This is because Ti capping layer increases reaction between Ni and Si and suppresses the oxidation and impurity incorporation into Ni film during silicidation process. The NiSi films were treated by additional thermal stress in a resistively heated furnace for test of thermal stability, showing that the film heat-treated at $800^{\circ}C$ was more stable than that at $700^{\circ}C$ due to better crystallinity.

• Korean Journal of Materials Research
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• v.25 no.5
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• pp.233-237
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• 2015

Silicon oxynitride that can be deposited two times faster than general SiNx:H layer was applied to fabricate the passivation protection layer of atomic layer deposition (ALD) $Al_2O_3$. The protection layer is deposited by plasma-enhanced chemical vapor deposition to protect $Al_2O_3$ passivation layer from a high temperature metallization process for contact firing in screen-printed silicon solar cell. In this study, we studied passivation performance of ALD $Al_2O_3$ film as functions of process temperature and RF plasma effect in plasma-enhanced chemical vapor deposition system. $Al_2O_3$/SiON stacks coated at $400^{\circ}C$ showed higher lifetime values in the as-stacked state. In contrast, a high quality $Al_2O_3$/SiON stack was obtained with a plasma power of 400 W and a capping-deposition temperature of $200^{\circ}C$ after the firing process. The best lifetime was achieved with stack films fired at $850^{\circ}C$. These results demonstrated the potential of the $Al_2O_3/SiON$ passivated layer for crystalline silicon solar cells.

• Journal of Korean Vacuum Science & Technology
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• v.4 no.3
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• pp.86-90
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• 2000

ZnO : Al films were prepared through the optimization process of aluminum content and substrate temperature in rf-magnetron sputtering. When hydrogenation was performed on these films using a hot filament method, all films showed improvement in conductivity although more conductive film showed less improvement. When the substrate temperature ($T_H$) was varied from $25^{\circ}C\;to\;300^{\circ}C$ during hydrogenation, the resistivity was reduced more at higher $T_H$ (more than 30% at $T_H=300^{\circ}C$) Thus, two methods were developed to suppress the dehydrogenation in ZnO : Al films : (1) capping with amorphous silicon thin film as a diffusion barrier, and (2) cooling during hydrogenation.

• Journal of Information Display
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• v.3 no.1
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• pp.11-16
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• 2002

This paper presents a study on the tubeless Plasma Display Panel (PDP) packaging using glass-to-glass electrostatic bonding with intermediate amorphous silicon. The bonded sample sealing the mixed gas with three species showed high strength ranging from 2.5 MPa to 4 MPa. The glass-to-glass bonding for packaging was performed at a low temperature of $180^{\circ}C$ by applying bias of 250 $V_{dc}$ in ambient of mixed gases of He-Ne(27 %)-Xe(3 %). The tubeless packaging was accomplished by bonding the support glass plate of $30mm{\times}50mm$ on the rear glass panel and the capping glass of $20mm{\times}20mm$. The 4-inch color AC-PDP with thickness of 8 mm was successfully fabricated and fully emitted as white color at a firing voltage of 190V.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11b
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• pp.205-208
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• 2001

Steady state and transient thermal analysis has been done by a finite element method in a diode of 12kV blocking voltage for microwave oven. The diode was fabricated by soldering ten pieces of 1200V diodes in series, capping a dummy wafer at the far end of diode series, and finally copper wire bonded for building anode and cathode terminal. In order to achieve high voltage and reliability, the edge of each diode was beveled and passivated by resin and epoxy with a thickness of $25{\mu}m$ and $3700{\mu}m$, respectively. The chip size, thickness and material properties were very important factor for high voltage diode package. And also, thermal stress value was highest in the edge of diode and solder. So, design of edge in silicon was very important to thermal stress.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.11a
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• pp.3-4
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• 2005

Germanium nanocrystals(NCs) were formed in the silicon dioxide($SiO_2$) on Si layers by Ge implantation and rapid thermal annealing process. The density and mean size of Ge-NCs heated at $800^{\circ}C$ during 10 min were confirmed by High Resolution Transmission Electron Microscopy. Capacitance versus voltage(C-V) measurements of MOS capacitors with single $Al_2O_3$ capping layers were performed in order to study electrical properties. The C-V results exhibit large threshold voltage shift originated by charging effect in Ge-NCs, revealing the possibility that the structure is applicable to Nano Floating Gate Memory(NFGM) devices.

• Transactions on Electrical and Electronic Materials
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• v.9 no.2
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• pp.47-51
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• 2008

In this paper, thermal stability of Nickel silicide formed on p-type silicon wafer using Ni-V alloy film was studied. As compared with pure Ni, Ni-V shows better thermal stability. The addition of Vanadium suppresses the phase transition of NiSi to $NiSi_2$ effectively. Ni-V single structure shows the best thermal stability compared with the other Ni-silicide using TiN and Co/TiN capping layers. To enhance the thermal stability up to $650^{\circ}C$ and find out the optimal thickness of Ni silicide, different thickness of Ni-V was also investigated in this work.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.5
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• pp.1029-1034
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• 2012

This paper presents a cost-effective and high-performance film bulk acoustic resonator (FBAR) duplexer module for US-PCS handset applications. The FBAR device uses a glass wafer level packaging process, which is a more cost-effective alternative to the typical silicon capping process. The maximum insertion losses of the FBAR duplexer at the Tx and Rx bands are of 1.9 and 2.4 dB, respectively. The total thickness of the duplexer module is 1.2 mm, including the glass-wafer bonded Tx/Rx FBAR devices, PCB board, and transfer molding material.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11a
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• pp.205-208
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• 2001

Steady state and transient thermal analysis has been done by a finite element method in a diode of 12kV blocking voltage for microwave oven. The diode was fabricated by soldering ten pieces of 1200V diodes in series, capping a dummy wafer at the far end of diode series, and finally copper wire bonded for building anode and cathode terminal. In order to achieve high voltage and reliability, the edge of each diode was beveled and passivated by resin and epoxy with a thickness of 25$\mu\textrm{m}$ and 3,700$\mu\textrm{m}$, respectively. The chip size, thickness and material properties were very important factor for high voltage diode package. And also, thermal stress value was highest in the edge of diode and solder. So, design of edge in silicon was very important to thermal stress.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.603-606
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• 2005

In this paper, the formation and thermal stability of Ni-silicide using Ni-Pd alloys is studied for ultra shallow S/D junction of nano-scale CMOSFETs. There are no different effects when Ni-Pd is used in single structure and TiN capping structure. But, in case of Cobalt interlayer structure, it was found that Pure Ni had lower sheet resistance than Ni-Pd, because of a thick silicide. Also, Ni-Pd has merits that surface of silicide and interface between silicide and silicon have a good morphology characteristics. As a result, Ni-Pd is an optimal candidate for shallow S/D junction when cobalt is used for thermal stability.