• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.11
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• pp.1434-1444
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• 1995

Current test has recently been known to be a promising testing method in CMOS VLSI because conventional voltage test can not make sure of the complete detection of bridging, gate-oxide shorts, stuck-open faults and etc. This paper presents a new BIC(built-in current sensor) for the internal current test in CMOS logic circuit. A single phase clock is used in the BIC to reduce the control circuitry of it and to perform a self- testing for a faulty current. The BIC is designed to detect the faulty current at the end of the clock period, so that it can test the CUT(circuit under test) with much longer critical propagation delay time and larger area than conventional BICs. The circuit is composed of 18 devices and verified by using the SPICE simulator.

• ETRI Journal
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• v.32 no.4
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• pp.642-644
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• 2010

With the rapid increase occurring in both the capacity and density of memory products, test and repair issues have become highly challenging. Memory repair is an effective and essential methodology for improving memory yield. An SoC utilizes built-in redundancy analysis (BIRA) with built-in self-test for improving memory yield and reliability. This letter proposes a new heuristic algorithm and new hardware architecture for the BIRA scheme. Experimental results indicate that the proposed algorithm shows near-optimal repair efficiency in combination with low area and time overheads.

• Journal of Korean Society for Quality Management
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• v.21 no.2
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• pp.1-16
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• 1993

Early generations of products had little to no inherent capability to test themselves. The technologies involved often required only visual inspection and limited probing to troubleshoot the system once it was turned over to maintenance personnel. However, as the complexity of military and commercial systems grew, symptoms of failure became less noticeable to the operator. Therefore, the procedure to access, inspect, repair and replace a component became complicated, the requirements for personnel skill and testing equipment increased. and it took too long of a time to maintain a system. Meanwhile, the need for availability became more mission-critical and maintenance become very expensive. The obvious solution was to design in-system circuits or devices to self-test the primary system, the Built-In-Test(BIT) was born. This approach has continued right on up through present systems and is an integral part of systems now being designed. The object of this paper is to present a state-of-the-art research for filtering out the BIT diagnosis mistakes using Bayesian analysis and develop the algorithm for Redundant systems with BIT to improve BIT diagnosis.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.49 no.6
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• pp.322-329
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• 2000

BIST(Built-in Self Test) has been considered as the most promising DFT(design-for-test) scheme for the present and future test strategy. The most serious problem in applying BIST(Built-in Self Test) into a large circuit is the excessive increase in test time. This paper is focused on this problem. We proposed a new BIST construction scheme which uses a parallel divide-and-conquer method. The circuit division is performed with respect to some internal nodes called test points. The test points are selected by considering the nodal connectivity of the circuit rather than the testability of each node. The test patterns are generated by only one linear feedback shift register(LFSR) and they are shared by all the divided circuits. Thus, the test for each divided circuit is performed in parallel. Test responses are collected from the test point as well as the primary outputs. Even though the divide-and-conquer scheme is used and test patterns are generated in one LFSR, the proposed scheme does not lose its pseudo-exhaustive property. We proposed a selection procedure to find the test points and it was implemented with C/C++ language. Several example circuits were applied to this procedure and the results showed that test time was reduced upto 1/2151 but the increase in the hardware overhead or the delay increase was not much high. Because the proposed scheme showed a tendency that the increasing rates in hardware overhead and delay overhead were less than that in test time reduction as the size of circuit increases, it is expected to be used efficiently for large circuits as VLSI and ULSI.

• ETRI Journal
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• v.35 no.1
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• pp.109-119
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• 2013

Static testing of analog-to-digital (A/D) and digital-to-analog (D/A) converters becomes more difficult when they are embedded in a system on chip. Built-in self-test (BIST) reduces the need for external support for testing. This paper proposes a new static BIST structure for testing both A/D and D/A converters. By sharing test circuitry, the proposed BIST reduces the hardware overhead. Furthermore, test time can also be reduced using the simultaneous test strategy of the proposed BIST. The proposed method can be applied in various A/D and D/A converter resolutions and analog signal swing ranges. Simulation results are presented to validate the proposed method by showing how linearity errors are detected in different situations.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.3
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• pp.226-232
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• 2002

This paper explains a technique to improve the fault coverage of oscillation-test [1-5] for linear analog circuits. The transient behavior of the virtual ground is monitored during oscillation to extract information of the circuit. The limitation of the oscillation-test is analyzed, and an efficient signature analysis technique is proposed to maximize the fault coverage. The experimental result proves that the parametric fault coverage can be significantly increased by the proposed technique.

• ETRI Journal
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• v.32 no.1
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• pp.154-156
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• 2010

Oscillation-based testing of analog-to-digital converters represents a viable option for low-cost built-in self-testing in mixed-signal design. While numerous papers have addressed implementation issues, little attention has been paid to the measurement accuracy. In this letter, we highlight an inherent measurement uncertainty which has to be considered when deriving the parameters from the oscillation frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.8
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• pp.55-62
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• 2012

The development of memory design and process technology enabled the production of high density memory. As the weight of embedded memory within aggregate Systems-On-Chips(SoC) gradually increases to 80-90% of the number of total transistors, the importance of testing embedded dual-port memories in SoC increases. This paper proposes a new micro-code based programmable memory Built-In Self-Test(PMBIST) architecture for dual-port memories that support test various test algorithms. In addition, various test algorithms including March based algorithms and dual-port memory test algorithms are efficiently programmed through the proposed algorithm instruction set. This PMBIST has an optimized hardware overhead, since test algorithm can be implemented with the minimum bits by the optimized algorithm instructions.

• Steel and Composite Structures
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• v.42 no.4
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• pp.513-538
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• 2022

This paper reports on experiments addressing the buckling and collapse behavior of an innovative built-up cold-formed steel (CFS) columns. The built-up column consists of four individual CFS lipped channels, two of them placed back-to-back at the web using two self-drilling screw fasteners at specified spacing along the column length, while the other two channels were connected flange-to-flange using one self-drilling screw fastener at specified spacing along the column length. In total, 12 experimental tests are reported, covering a wide range of column lengths from stub to slender columns. The initial geometric imperfections and material properties were determined for all test specimens. The effect of screw spacing, load-versus axial shortening behaviour and buckling modes for different lengths and screw spacing were investigated. Nonlinear finite element (FE) models were also developed, which included material nonlinearities and initial geometric imperfections. The FE models were validated against the experimental results, both in terms of axial capacity and failure modes of built-up CFS columns. Furthermore, using the validated FE models, a parametric study was conducted which comprises 324 models to investigate the effect of screw fastener spacing, thicknesses and wide range of lengths on axial capacity of back-to-back and flange-to-flange built-up CFS channel sections. Using both the experimental and FE results, it is shown that design in accordance with the American Iron and Steel Institute (AISI) and Australia/New Zealand (AS/NZS) standards is slightly conservative by 6% on average, while determining the axial capacity of back-to-back and flange-to-flange built-up CFS channel sections.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.1A
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• pp.66-72
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• 2002

In this paper, we implemented the GenJTAG, a CAD tool, which generates a code of boundary scan circuit supporing a board level testing and d BIST(Built-In Self Test) written in verilog-HDL. A boundary scan circuit code that supports user's own BIST instructions is generated based on the informations from the users. Most CAD tools hardly allow users to add their own BIST instructions because the generated code described in gate-level. But the GenJTAG generates a behavioral boundary scan circuit code so users can easily make a change on the generated code.