• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.7
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• pp.12-18
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• 1993

We have proposed a soft-decision decoding method for block codes. With careful examinations of the first hard-decision decoded results, The candidate codewords are efficiently searched for. Thus, we can reduce the decoding complexity (the number of hard-decision decodings) and lower the block error probability. Computer simulation results are presented for the (23,12) Golay code. They show that the decoding complexity is considerably reduced and the block error probability is close to that of the maximum likelihood decoder.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.803-806
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• 2003

본 논문에서는 traceback 동작 없이 decoding이 가능한 Modified Register Exchange 방식을 이용하여 이를 block decoding에 적용하는 비터비 decoding 방식을 제안하였다. Modified Register Exchange 방식을 block decoding에 적용함으로써 decision bit 들을 결정하기 위해 필요한 동작 사이클을 줄였고, block decoding을 사용하는 기존의 비터비 디코더보다 더 적은 latency 가지게 되었다. 뿐만 아니라, 메모리를 더 효율적으로 사용할 수 있으면서 하드웨어의 구현에 있어서도 복잡도가 더 감소하게 된다. 제안된 방식은 같은 하드웨어 복잡도로도 메모리의 감소 또는 latency 의 감소에 중점을 둔 설계가 가능하다.

• Journal of Broadcast Engineering
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• v.16 no.6
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• pp.1026-1035
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• 2011

This paper presents generalization and application for the conventional SISO decoding algorithm of Block Turbo Codes. R. M. Pyndiah suggested an iterative SISO decoding algorithm for Product Codes, two-dimensionally combined linear block codes, on AWGN channel. It wascalled Block Turbo Codes. Based on decision of Chase algorithm which is SIHO decoding method, SISO decoder for BTC computes soft decision information and transfers the information to next decoder for iterative decoding. Block Turbo Codes show Shannon limit approaching performance with a little iteration at high code rate on AWGN channel. In this paper we generalize the conventional decoding algorithm of Block Turbo Codes, under BPSK modulation and AWGN channel transmission assumption, to the LLR value based algorithm and suggest an application example such as concatenated structure of LDPC codes and Block Turbo Codes.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.8
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• pp.3749-3768
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• 2018

As one of the most potential types of low-density parity-check (LDPC) codes, CPM-QC-LDPC code has considerable advantages but there still exist some limitations in practical application, for example, the existing decoding algorithm has a low convergence rate and a high decoding complexity. According to the structural property of this code, we propose a new method based on a CPM-RID decoding algorithm that decodes block-by-block with weights, which are obtained by neural network training. From the simulation results, we can conclude that our proposed method not only improves the bit error rate and frame error rate performance but also increases the convergence rate, when compared with the original CPM-RID decoding algorithm and scaled MSA algorithm.

• IEIE Transactions on Smart Processing and Computing
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• v.6 no.3
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• pp.210-219
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• 2017

This paper proposes a modified min-max algorithm (MMMA) for nonbinary quasi-cyclic low-density parity-check (NB-QC-LDPC) codes and an efficient parallel block-layered decoder architecture corresponding to the algorithm on a graphics processing unit (GPU) platform. The algorithm removes multiplications over the Galois field (GF) in the merger step to reduce decoding latency without any performance loss. The decoding implementation on a GPU for NB-QC-LDPC codes achieves improvements in both flexibility and scalability. To perform the decoding on the GPU, data and memory structures suitable for parallel computing are designed. The implementation results for NB-QC-LDPC codes over GF(32) and GF(64) demonstrate that the parallel block-layered decoding on a GPU accelerates the decoding process to provide a faster decoding runtime, and obtains a higher coding gain under a low $10^{-10}$ bit error rate and low $10^{-7}$ frame error rate, compared to existing methods.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.11C
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• pp.907-910
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• 2010

This paper presents the design of block lengths for irregular low-density parity-check (LDPC) codes based on the maximum variable degree $d_{{\upsilon},max}$. To design a block length, the performance degradation of belief-propagation (BP) decoding performance from upper bounds on the maximum likelihood (ML) decoding performance is used as an important factor. Since for large block lengths, the performance of irregular LDPC codes is very close to the Shannon limit, we focus on moderate block lengths ($5{\times}10^2\;{\leq}\;N\;{\leq}\;4{\times}10^3$). Given degree distributions, the purpose of our paper is to find proper block lengths based on the maximum variable degree $d_{{\upsilon},max}$. We also present some simulation results which show how a block length can be optimized.

• ETRI Journal
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• v.25 no.1
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• pp.1-8
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• 2003

This paper introduces an efficient iterative decoding method for high-dimensional block turbo codes. To improve the decoding performance, we modified the soft decision Viterbi decoding algorithm, which is a trellis-based method. The iteration number can be significantly reduced in the soft output decoding process by applying multiple usage of extrinsic reliability information from all available axes and appropriately normalizing them. Our simulation results reveal that the proposed decoding process needs only about 30% of the iterations required to obtain the same performance with the conventional method at a bit error rate range of $10^{-5}\;to\;10^{-6}$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.8A
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• pp.725-732
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• 2002

Block-wise MAP (Maximum A posteriori) decoding algorithm for turbo-codes requires less memory than Log-MAP decoding algorithm. The ER (Bit Error Rate) performance of previous block-wise MAP decoding algorithm depend on the block length and training length. To maximize hardware utilization and perform successive decoding, the block length is set to be equal to the training length in previous MAP decoding algorithms. Simulation result on the BER performance shows that the EBR performance can be maintained with shorter blocks when training length is sufficient. This paper proposes an architecture for area efficient block-wise MAP decoder. The proposed architecture employs the decoding schema for reducing memory by using the training length, which in N times larger than block length. To efficiently handle the proposed schema, a pipelined architecture is proposed. Simulation results show that memory usage can be reduced by 30%~45% in the proposed architecture without degrading the BER performance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.11C
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• pp.880-882
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• 2008

This paper presents LDPC codes' upper bounds over the waterfall SNR region. The previous researches have focused on the average bound or ensemble bound over the whole SNR region and showed the performance differences for the fixed block size. In this paper, the particular LDPC codes' upper bounds for various block sizes are calculated over the waterfall SNR region and are compared with BP decoding performance. For different block sizes the performance degradation of BP decoding is shown.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.2
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• pp.9-15
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• 1990

A soft-decision decoding algorithm for linear binary block codes is proposed, for minimizing the block error probability. To compare the proposed algorithm with already established decoding methods, computer simulations are performed for the (7,4)Hamming code and the (23,12) Golay code. The average number of hard-decision decoding is always less then 2, and approaches to 1 when the signal to noise ratio is sufficiently large. These results show that the proposed algorithm reduces the decoding complexity.