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Design of an Area-Efficient Architecture for Block-wise MAP Turbo Decoder  

Kang, Moon-Jun (서강대학교 전자공학과 CAD & Computer Systems 연구실)
Kim, Sik (서강대학교 전자공학과 CAD & Computer Systems 연구실)
Hwang, Sun-Young (서강대학교 전자공학과 CAD & Computer Systems 연구실)
Publication Information
The Journal of Korean Institute of Communications and Information Sciences / v.27, no.8A, 2002 , pp. 725-732 More about this Journal
Abstract
Block-wise MAP (Maximum A posteriori) decoding algorithm for turbo-codes requires less memory than Log-MAP decoding algorithm. The ER (Bit Error Rate) performance of previous block-wise MAP decoding algorithm depend on the block length and training length. To maximize hardware utilization and perform successive decoding, the block length is set to be equal to the training length in previous MAP decoding algorithms. Simulation result on the BER performance shows that the EBR performance can be maintained with shorter blocks when training length is sufficient. This paper proposes an architecture for area efficient block-wise MAP decoder. The proposed architecture employs the decoding schema for reducing memory by using the training length, which in N times larger than block length. To efficiently handle the proposed schema, a pipelined architecture is proposed. Simulation results show that memory usage can be reduced by 30%~45% in the proposed architecture without degrading the BER performance.
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