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http://dx.doi.org/10.5573/IEIESPC.2017.6.3.210

Efficient Parallel Block-layered Nonbinary Quasi-cyclic Low-density Parity-check Decoding on a GPU  

Thi, Huyen Pham (Department of Information and Communication Engineering, Inha University)
Lee, Hanho (Department of Information and Communication Engineering, Inha University)
Publication Information
IEIE Transactions on Smart Processing and Computing / v.6, no.3, 2017 , pp. 210-219 More about this Journal
Abstract
This paper proposes a modified min-max algorithm (MMMA) for nonbinary quasi-cyclic low-density parity-check (NB-QC-LDPC) codes and an efficient parallel block-layered decoder architecture corresponding to the algorithm on a graphics processing unit (GPU) platform. The algorithm removes multiplications over the Galois field (GF) in the merger step to reduce decoding latency without any performance loss. The decoding implementation on a GPU for NB-QC-LDPC codes achieves improvements in both flexibility and scalability. To perform the decoding on the GPU, data and memory structures suitable for parallel computing are designed. The implementation results for NB-QC-LDPC codes over GF(32) and GF(64) demonstrate that the parallel block-layered decoding on a GPU accelerates the decoding process to provide a faster decoding runtime, and obtains a higher coding gain under a low $10^{-10}$ bit error rate and low $10^{-7}$ frame error rate, compared to existing methods.
Keywords
NB-LDPC; Iterative decoding; GPU; Parallel computation; CUDA;
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