• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.11
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• pp.828-835
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• 2001

Novel bipolar transresistance amplifier(TRA) and its offset-compensated TRA for high-performance current-mode signal processing are described. The TRA consist of two current follower for a current inputs, a current summer for the current-difference, a resistor for the current to voltage converter, and a voltage follower for the voltage output. The offset-compensated TRA adopts diode-connected npn and pnp transistor to reduce offset voltage in the TRA. The simulation results show that the TRA has impedance of 0.5 Ω at the input and the output terminal. The offset voltages at these terminals is 40 mV The offset-compensated TRA has the offset voltage of 1.1 mV and the impedance of 0.25 Ω. The 3-dB cutoff frequency is 40 MHz for the two TRA＇s when used as a current to voltage converter with unit-gain transresistance. The power dissipation is 11.25 mW.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.39 no.10
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• pp.1011-1019
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• 2015

Insulated-gate bipolar transistors (IGBTs) are the predominantly used power semiconductors for high-current applications, and are used in trains, airplanes, electrical, and hybrid vehicles. IGBT power modules generate a considerable amount of heat from the dissipation of electric power. This heat generation causes several reliability problems and deteriorates the performances of the IGBT devices. Therefore, thermal management is critical for IGBT modules. In particular, realizing a proper thermal design for which the device temperature does not exceed a specified limit has been a key factor in developing IGBT modules. In this study, we investigate the thermal behavior of the 1200 A, 3.3 kV IGBT module package using finite-element numerical simulation. In order to minimize the temperature of IGBT devices, we analyze the effects of various packaging materials and different thickness values on the thermal characteristics of IGBT modules, and we also perform a design-of-experiment (DOE) optimization

• Journal of the Microelectronics and Packaging Society
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• v.21 no.3
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• pp.7-17
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• 2014

Power electronics modules are semiconductor components that are widely used in airplanes, trains, automobiles, and energy generation and conversion facilities. In particular, insulated gate bipolar transistors(IGBT) have been widely utilized in high power and fast switching applications for power management including power supplies, uninterruptible power systems, and AC/DC converters. In these days, IGBT are the predominant power semiconductors for high current applications in electrical and hybrid vehicles application. In these application environments, the physical conditions are often severe with strong electric currents, high voltage, high temperature, high humidity, and vibrations. Therefore, IGBT module packages involves a number of challenges for the design engineer in terms of reliability. Thermal and thermal-mechanical management are critical for power electronics modules. The failure mechanisms that limit the number of power cycles are caused by the coefficient of thermal expansion mismatch between the materials used in the IGBT modules. All interfaces in the module could be locations for potential failures. Therefore, a proper thermal design where the temperature does not exceed an allowable limit of the devices has been a key factor in developing IGBT modules. In this paper, we discussed the effects of various package materials on heat dissipation and thermal management, as well as recent technology of the new package materials.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.10
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• pp.754-764
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• 2001

Class A bipolar second-generation current conveyor (CCII) with low current-input impedance and its offset-compensated CCII for high-accuracy current-mode signal processing are proposed. The CCIIs consist of a regulated current-cell for current input, a emitter follower for voltage input, and a cascode current mirror lot current output. In these architecture, the two input stages are coupled by current mirror to reduce the current input impedance. Experiments show that the CCII has impedance of 8.4 Ω and offset voltage of 40 mV at current input terminal. To reduce this offset, the offset-compensated CCII adopts diode-connected npn and pnp transistor in the proposed CCII. Experiments show that the offset-compensated CCII has current input impedance of 2.1 Ω and offset voltage of 0.05 mV. The 3-dB cutoff frequency of the CCIIs when used as a voltage follower extends beyond 30 MHz. The power dissipation is 7.0 mW

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.3
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• pp.784-794
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• 1996

In this papre, the design and the fabrication of the surface mountable voltage controlled oscillator is described for local oscillator in PCS(WACS/TDMA) handset. The VCO employs two silicon bipolar transistors of $f_{gamma}$ of 4 GHz as active devices. These are asembled to form the VCO on the 4 layer PCB of the size $12{\times}10mm$which provides the strip line resonator at the third layer. The fabricated VCO shows tuning rage over 50 MHz, phase noise -100 dBc/Hz at the 100 kHz frequency offset, and 0 dBm output power with the consumption of 22 mA at 3V. It is belived that the size will be more reduced by employing 1005 chip components and that the current consumption will be improved by employing transistors of higher $f_{gamma}$.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.2
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• pp.71-82
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• 1984

A programme, called BIPOLE, for the numerical analysis of twotimensional n-p-n bipolar transistors was developed. It has included the SRH and Auger recolnbination processes, the mobility dependence on the impurity density and the electric field, and the band-gap narrowing effect. The finite difference equations of the fundamental semiconductor equations are formulated using Newton's method for Poisson's equation and the divergence theorem for the hole and electron continuity equations without physical restrictions. The matrix of the linearized equations is sparse, symmetric M-matrix. For the solution of the linearized equations ICCG method and Gummel's algorithm have been employed. The programme BIPOLE has been applied to various kinds of the steady-state problems of n-p-n transistors. For the examples of applications the variations of common emitter current gain, emitter and diffusion capacitances, and input and output characteristics are calculated. Three-dimensional representations of some D.C. physical quantities such as potential and charge carrier distributions were displayed. This programme will be used for the nome,rical analysis of the distortion phenom ana of two-dimensional n-p-n transistors. The BIPOLE programme is available for everyone.

• Journal of the Korean Vacuum Society
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• v.14 no.4
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• pp.229-237
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• 2005

The degradation phenomena in SiGe hetero-junction bipolar transistors(SiGe HBTs) induced by bias stress are investigated in this review. If SiGe HBTs are stressed over a specific time interval, the device parameters deviate from their nominal values due to the internal changes in the devices. Reverse-bias stress on emitter-base(EB) junctions causes base current increase and current gain decrease because carriers accelerated by the electrical field generate recombination centers. When forward-bias current stress is conducted at an ambient temperature above $140^{\circ}C$ , hot carriers produced by Auger recombination or avalanche multiplication induce current gain fluctuation. Mixed-mode stressing, where high emitter current and high collector-base voltage are simultaneously applied to the device, provokes base current rise as EB reverse-bias stressing does.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.31 no.6
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• pp.377-385
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• 2018

For the investigation of dopant profiles in implanted $Si_{1-x}Ge_x$, the implanted B and As profiles are measured using SIMS (secondary ion mass spectrometry). The fundamental ion-solid interactions of implantation in $Si_{1-x}Ge_x$ are discussed and explained using SRIM, UT-marlowe, and T-dyn programs. The annealed simulation profiles are also analyzed and compared with experimental data. In comparison with the SIMS data, the boron simulation results show 8% deviations of $R_p$ and 1.8% deviations of ${\Delta}R_p$ owing to relatively small lattice strain and relaxation on the sample surface. In comparison with the SIMS data, the simulation results show 4.7% deviations of $R_p$ and 8.1% deviations of ${\Delta}R_p$ in the arsenic implanted $Si_{0.2}Ge_{0.8}$ layer and 8.5% deviations of $R_p$ and 38% deviations of ${\Delta}R_p$ in the $Si_{0.5}Ge_{0.5}$ layer. An analytical method for obtaining the dopant profile is proposed and also compared with experimental and simulation data herein. For the high-speed CMOSFET (complementary metal oxide semiconductor field effect transistor) and HBT (heterojunction bipolar transistor), the study of dopant profiles in the $Si_{1-x}Ge_x$ layer becomes more important for accurate device scaling and fabrication technologies.

• Journal of the Korean Society of Safety
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• v.36 no.2
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• pp.10-17
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• 2021

This paper presents the robust design of each component used in the development of an induction bolt heating system for dismantling the high-temperature high-pressure casing heating bolts of turbines in power plants. The induction bolt heating system comprises seven assemblies, namely AC breaker, AC filter, inverter, transformer, work coil, cable, and CT/PT. For each of these assemblies, the various failure modes are identified by the failure mode and effects analysis (FMEA) method, and the causes and effects of these failure modes are presented. In addition, the risk priority numbers are deduced for the individual parts. To ensure robust design, the insulated-gate bipolar transistor (IGBT), switched-mode power supply (SMPS), C/T (adjusting current), capacitor, and coupling are selected. The IGBT is changed to a field-effect transistor (FET) to enhance the voltage applied to the induction heating system, and a dual-safety device is added to the SMPS. For C/T (adjusting current), the turns ratio is adjusted to ensure an appropriate amount of induced current. The capacitor is replaced by a product with heat resistance and durability; further, coupling with a water-resistant structure is improved such that the connecting parts are not easily destroyed. The ground connection is chosen for management priority.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.1
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• pp.40-48
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• 2000

1A novel bipolar linear transconductor and its application to operational transconductance amplifier(OTA) for low-voltage low-power signal processing is proposed. The transconductor consists of a npn differential-pair with emitter degeneration resistor and a pnp differential-pair connected to the npn differential-pair in cascade. The bias current of the pnp differential-pair is used with the output current of the npn differential-pair for wide linearity and temperature stability. The OTA consists of the linear transconductor and a translinear current cell followed by three current mirrors. The proposed transconductor has superior linearity and low-voltage low-power characteristics when compared with the conventional transconductor. The experimental results show that the transconductor with transconductance of 50 ${\mu}S$ has a linearity error of less than ${\pm}$0.06% over an input voltage range from -2V to +2V at supply voltage ${\pm}$3V. Power dissipation of the transconductor was 2.44 mW. A prototype OTA with a transconductance of 25 ${\mu}S$ has been built with bipolar transistor array. The linearity of the OTA was same as the proposed transconductor. The OTA circuit also exhibits a transconductance that is linearly dependent on a bias current varying over four decades with a sensitivity of 0.5 S/A.