• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.11
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• pp.1619-1626
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• 2021

Unlike traditional delta-sigma analog-to-digital converters, incremental analog-to-digital converters enable 1:1 mapping of input and output through a reset operation, which can be used very easily for multiplexing. Incremental analog-to-digital converters also allow for simpler digital filter designs compared to traditional delta-sigma converters. Therefore, starting with analysis in the time domain of the delayed integrator and non-delayed integrator, which are the basic blocks of analog-to-digital converter design, the design equations of a second-order input feed-forward, extended counting, 2+1 MASH (Multi-stAge-noise-SHaping), 2+2 MASH incremental analog-to-digital converter are derived in this paper. This allows not only prediction of the performance of the incremental analog-to-digital converter before design, but also the design of a digital filter suitable for each analog-to-digital converter. In addition, extended counting and MASH design techniques were proposed to improve the accuracy of analog-to-digital converters.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.9
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• pp.57-63
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• 1998

This paper describes a CMOS digital-to-analog converter to apply a newly-developed digital-to-analog conversion algorithm. The CMOS digital-to-analog converter has been designed by using 1.2$\mu\textrm{m}$ MOSIS SCMOS parameter and simulated for the performance. The simulated results have shown that the digital-to-analog converter has 200MHz of the maximum conversion rate, 7.41mW of the DC power consumption, and ${\pm}$0.08LSB of INL and ${\pm}$0.098LSB of DNL in 8-b.

• Progress in Superconductivity and Cryogenics
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• v.4 no.1
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• pp.8-12
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• 2002

Since the high performance analog-to-digital converter can be built with Rapid Single Flux Quantum (RSFQ) logic circuits the development of superconductive analog-to-digital converter has attracted a lot of interests as one of the most prospective area of the application of Josephson Junction technology. One of the main advantages in using Rapid Sng1e Flux Quantum logic in the analog-to-digital converter is the low voltage output from the Josephson junction switching, and hence the high resolution. To design an analog-digital converter, first we have used XIC tool to compose a circuit schematic, and then studied the operational principle of the circuit with WRSPICE tool. Through this process, we obtained the proper circuit diagram of an 1-bit analog-digital converter circuit. The optimized circuit was laid out as a mask drawing. Inductance values of the circuit layout were calculated with L-meter.

• Current Optics and Photonics
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• v.4 no.6
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• pp.483-499
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• 2020

In this paper, a novel analog signature scheme is proposed by modifying an RSA-based digital signature scheme with optical phase-shifting digital holography. The purpose of the proposed method is generating an analog signature to provide data confidentiality and security during the data transfer, compared to the digital signature. The holographic encryption technique applied to a hash value reveals an analog-type of pseudo-random pattern in the analog signature scheme. The public key and secret key needed to verify the analog signature are computed from public key ciphers which are generated by the same holographic encryption. The proposed analog signature scheme contains a kind of double encryption in the process of generating signature and key, which enhances security level more than the digital signature. The results of performance simulations show the feasibility of the highly secure signature scheme, and security analysis shows high robustness against known-message attacks and chosen-message attacks. In addition, the proposed method can apply to one-time signature schemes which can be used to sign only one message and it can also apply to authentication, e-mails, electronic banking and electronic data interchange.

• IEMEK Journal of Embedded Systems and Applications
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• v.14 no.1
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• pp.33-41
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• 2019

We propose an embedded solution to design a high-speed and high-accuracy 16bit analog-digital signal processing interface for the control systems using various external analog signals. Choosing TMS320F28377D micro controller unit (MCU) featuring high-performance processing in the 32-bit floating point operation, low power consumption, and various I/O device supports, we design and build the proposed system that supports both 16-bit analog-digital converter (ADC) interface and high precision digital-analog converter (DAC) interface. The ADC receives voltage-level differential signals from fully differential amplifiers, and the DAC communicates with MCU through 50 MHz bandwidth high-fast serial peripheral interface (SPI). We port the boot loader and device drivers to the implemented board, and construct the firmware development environment for the application programming. The performance of the entire implemented system is demonstrated by analog-digital signal processing tests, and is verified by comparing the test results with those of existing similar systems.

• Journal of IKEEE
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• v.25 no.2
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• pp.302-308
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• 2021

A 12-bit 10-MS/s pipeline analog-to-digital converter (ADC) is proposed for image processing applications. The proposed pipeline ADC consists of a sample and hold amplifier, three stages, a 3-bit flash analog-to-digital converter, and a digital error corrector. Each stage is operated by using a 4-bit flash ADC (FADC) and a multiplying digital-to-analog converter (MDAC). The proposed sample and hold amplifier increases the voltage gain using gain boosting for the ADC with high resolution. The proposed pipelined ADC is designed using a 180-nm CMOS process with a supply voltage of 1.8 and it has an effective number of bit (ENOB) of 10.52 bits at sampling rate of 10MS/s for a 1-V_pp differential sinusoidal analog input with frequency of 1 MHz. The measured ENOB is 10.12 bits when the frequency of the sinusoidal analog input signal is a Nyquist frequency of approximately 5 MHz.

• Journal of information and communication convergence engineering
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• v.15 no.4
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• pp.232-236
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• 2017

A digital vacuum pressure sensor is designed, fabricated, and characterized using a packaged MEMS analog Pirani gauge. The packaged MEMS analog Pirani gauge requires a current source to heat up a heater in the Pirani gauge. To investigate the feasibility of digitization for the analog Pirani gauge, its implementation is performed with a zero-temperature coefficient current source and microcontroller that are commercially available. The measurement results using the digital vacuum pressure sensor showed that its operating range is 0.05-760 Torr, which is the same as the measurement results of the packaged MEMS analog pressure sensor. The results confirm that it is feasible to integrate the analog Pirani gauge with a commercially available current source and microcontroller. The successful hybrid integration of the analog Pirani gauge and digital circuits is an encouraging result for monolithic integration with a precision current source and ADCs in the state of CMOS dies.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.11 no.5
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• pp.315-322
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• 1986

In this paper, we have studied on the IIR digital filters design using Elliptic functions. In process of transformation to digital fouctions from analos Elliptic functions, Bilinear z transformation method has been silized. Designing of digital filter using the Bilinear z transformation the problems of aliasing can be avoidedm whereas the frequency distrotion is generated. The transformation form analog function to digital function is not equal in the region of the cut off frequency response caused by this effect. Avoiding the problem of this effect, we have used proewarping method. Finally, the magnitude characteristics of digital filters are compared with its of analog filters by computer simulation. The results have shown that the magnitude characteristics of digital filters by the prewarping method have made more remarkable improvement than its of analog filters.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.1
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• pp.129-134
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• 2014

This paper presents a 10-bit 10-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) which consists of a digital-to-analog converter (DAC), a SAR logic, and a comparator. The designed asynchronous SAR ADC with a rail-to-rail input range uses a binary weighted DAC using metal-oxide-metal (MOM) capacitor to improve sampling rate. The proposed 10-bit 10-MS/s asynchronous SAR ADC is fabricated using a 0.18-${\mu}m$ CMOS process and its active area is $0.103mm^2$. The power consumption is 0.37 mW when the voltage of supply is 1.1 V. The measured SNDR are 54.19 dB and 51.59 dB at the analog input frequency of 101.12 kHz and 5.12 MHz, respectively.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1229-1232
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• 2003

In this paper, The High-speed Low-power Analog-to-Digital Convener Archecture is proposed using the parallel S/H for High-speed operation. This technique can significantly reduce the sampling frequency per S/H channel. The Analog-to-Digital Converter is designed using 0.35${\mu}{\textrm}{m}$ CMOS technology. The simulation result show that the proposed Analog-to-Digital Converter can be operated at 40Ms/s with 8-bit resolution and INL/DNL errors are +0.4LSB~-0.6LSB / +0.9LSB~-1.4LSB , respectively.