• 천문학논총
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• 제22권3호
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• pp.63-73
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• 2007

In this paper, we introduce the performance test results of digital data processing system for KVN (Korean VLBI Network). The digital data processing system for KVN consists of DAS (Data Acquisition System) and high-speed recorder which called Mark5B system. DAS system performs the digitalization of analog radio signal through ADS-1000 gigabit sampler with 1 Gsps/2-bit and process the digital filtering of digital signal. Mark5B system records the output data of DFB (Digital Filter Bank) with about 1 Gbps. In this paper, we carried out the preliminary evaluation experiments of the KVN digital data processing system connected between DAS system and Mark5B with VSI (VLBI Standard Interface) interface which is designed for compatible in each VLBI system. We first performed all of the KVN digital data processing system connected by VSI interface in the world. In factory inspection phase, we found that the DAS system has a memory read/write error in DSM (Digital Spectrometer) by analyzing the recorded data in Mark5B system. We confirmed that the DSM memory error has been correctly solved by comparing DSM results with Mark5B results. The effectiveness of KVN digital data processing system has been verified through the preliminary experiments such as data transmission, recording with VSI interface connection and data analysis between DSM and Mark5B system. In future work, we will perform the real astronomical observation by using the KVN 21m radio telescopes so as to verify its stability and performance.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2010년도 추계학술대회
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• pp.84-87
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• 2010

본 논문에서는 power management IC에 사용되는 아날로그 트리밍용 antifuse OTP 셀을 제작하였다. VPP (=7V)와 VNN (=-5V)의 Dual program voltage를 이용하는 antifuse OTP 셀은 antifuse 양단에 hard breakdown 이상의 전압을 인가하여 thin gate oxide를 breakdown시킨다. $0.18{\mu}m$ BCD 공정을 이용하여 제작된 antifuse OTP 셀의 면적은 $48.01{\mu}m^2$으로 eFuse OTP 셀 면적의 44.6% 수준이다. 20개의 테스트 패턴을 측정한 결과 프로그램 후 antifuse의 저항은 수 $k{\Omega}$ 이하로 양호하게 측정되었다.

• 전기전자학회논문지
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• 제28권1호
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• pp.78-89
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• 2024

차량용 반도체에서 사용되는 BCD 공정 기반의 PMIC 칩은 아날로그 회로를 트리밍하기 위해 추가 마스크가 필요없는 MTP(Multi-Time Programmable) IP(Intellectual Property)를 요구한다. 본 논문에서는 저면적 MTP IP 설계를 위해 2개의 트랜지스터와 1개의 MOS 커패시터를 갖는 single poly EEPROM 셀인 MTP 셀에서 NCAP(NMOS Capacitor) 대신 PCAP(PMOS Capacitor)을 사용한 MTP 셀을 사용하여 MTP 셀 사이즈를 18.4% 정도 줄였다. 그리고 MTP IP 회로 설계 관점에서 MTP IP 설계의 CG 구동회로와 TG 구동회로에 2-stage voltage shifter 회로를 적용하였고, DC-DC 변환기 회로의 면적을 줄이기 위해 전하 펌핑 방식을 사용하는 VPP(=7.75V), VNN(=-7.75V)와 VNNL(=-2.5V) 전하 펌프 회로에서 각각의 전하 펌프마다 별도로 두고 있는 ring oscillator 회로를 하나만 둔 회로를 제안하였으며, VPPL(=2.5V)은 전하펌프 대신 voltage regulator 회로를 사용하는 방식을 제안하였다. 180nm BCD 공정 기반으로 설계된 4Kb MTP IP 사이즈는 0.493mm²이다.

• 한국해양공학회:학술대회논문집
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• 한국해양공학회 2003년도 추계학술대회 논문집
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• pp.336-339
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• 2003

A digital data logging system has been developed for the purpose of a compact offline Ocean Bottom Seismometer(OBS). The Digital Data Logger(DDL) consists of A/D system, Micom with storage memory and firmware managing data files. The A/D system acquires data of 16bit/4ch with sampling rate of 250Hz per channel. The Micom, a micro controller board with T33521 processor of 8051 class, was equipped with 8 flash memories of 128MB for data storage capacity of 1GB. The firmware stores the acquiring data in form of binary files. The DDL was designated to be compact and light and to consume low energy as possible. The DDL is to interface with PC through USB(Universal Serial Bus). The performance of the DDL has been validated through tests with respect to a 3-axis seismometer.

• 한국전자파학회:학술대회논문집
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• 한국전자파학회 2003년도 종합학술발표회 논문집 Vol.13 No.1
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• pp.213-218
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• 2003

Because of the development of digital technology, modern digital instrumentation & control systems are being innovativly developed in industrial plants. Whereas, many analog systems are still being used in nuclear plants, because of the demerits of digital equipment. As known, the demerits of digital equipment are the uncertainty and weaknesses in ambient environments such as smoke & electromagnetic interference In an Integral Reactor, a digital I&C system will be composed of microprocessor, memory and network card. Designers will apply new technique for digital equipment. Thus, it is important for digital I&C systems to operate according to designed functions & performance in the ambient environments during a life cycle. Digital I&C systems should have tolerance in such environments and environment qualification should be concluded To acquire electromagnetic interference qualification of digital equipment, this paper suggests an EMI test requirement. Designers should consider the electromagnetic compatibility and test digital equipment according to each test procedure. This paper involves an EMI test requirement and the results analysis of EUT(Equipment Under Test). Test result analysis will be used as electromagnetic compatibility design guides for Integral Reactor I&C systems.

• 전기전자학회논문지
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• 제21권3호
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• pp.260-263
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• 2017

다종의 CPU를 기반으로 ADC와 DC-DC 변환기를 포함하며 2M-byte의 SRAM이 내장된 SoC가 제안되었다. CPU 코어는 12-bit MENSA 코어, 32-bit Symmetric Multi-core 프로세서, 16-bit CDSP로 구성된다. 외부 SDRAM 메모리를 제거하기 위해 내부의 2M-byte SRAM을 설계하였으나 SRAM 블록들이 넓은 영역에 분포하여 기생 성분에 의해 속도가 저하되므로 SRAM을 작게 분할하여 레이아웃 하였다. 설계된 SoC는 55nm 공정으로 개발되었으며 속도는 200MHz이다.

• 대한전기학회논문지:시스템및제어부문D
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• 제54권9호
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• pp.531-538
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• 2005

This paper proposes an expert system which is able to enhance the accuracy and productivity by determining the test strategy based on heuristic rules for test of the hybrid electronic circuit board producted massively in production line. The test heuristic rules are obtained from test system designer, test experts and experimental results. The guarding method separating the tested device with circumference circuit of the device is adopted to enhance the accuracy of measurements in the test of analog devices. This guarding method can reduce the error occurring due to the voltage drop in both the signal input line and the measuring line by utilizing heuristic rules considering the device impedance and the parallel impedance. Also, PSA(Parallel Signature Analysis) technique Is applied for test of the digital devices and circuits. In the PSA technique, the real-time test of the high integrated device is possible by minimizing the test time forcing n bit output stream from the tested device to LFSR continuously. It is implemented in Visual C++ computer language for the purpose of the implementation of the inference engine using the dynamic memory allocation technique, the interface with the electronic circuit database and the hardware direct control. Finally, the effectiveness of the builded expert system is proved by simulating the several faults occurring in the mounting process the electronic devices to the surface of PCB for a typical hybrid electronic board and by identifying the results.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.511-512
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• 2007

The monitoring system has won acceptance as a premium mark that identifies the highest standard of product quality in advanced industry. The TOP features with multi-I/O ports and VGA & RCA TV-out ports supporting mirroring & multiple dual-display modes by windows 0/5. With the choice of versatile stands, panel mount, or VESA wall-mount swing arm and connecting to modem. Wireless keyboard, Customer Display and Card Reader, is your idea Panel system for the application of TOP(Touch Operation Pannel), KIOSK, or Office / Factory Automation. TOP is the hardware and software product that transacts all kind of functions for advanced technology equipment to button, switch, voice and graph etc so that let consumer use easily Industrial HMI System Touch Panel. System characteristics: Easy of use and flexibility to the user, Present a high value solution and advanced function for many Application, Factory Automation, Office Automation, Building Automation System, Information Service System, etc. Analog Touch - 2MB Flash Memory for Saving Screen Data - RS-232C/422 Serial Port - Multi Language Support.

• 인터넷정보학회논문지
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• 제5권2호
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• pp.1-15
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• 2004

현재의 인터넷 공간은 소위 유비쿼터스 공간으로 진화해 가고 있다. 인터넷 공간과는 달리, 유비쿼터스 공간에서는 정보가 컴퓨터 메모리, 인간의 두뇌 그리고 물리적 사물에 골고루 분포하게 된다. ‘하이퍼텍스트’ 는 컴퓨터 메모리(즉, 전자 공간)를 전제로 한 정보 연결 모델로, 유비쿼터스 공간에는 잘 맞지 않는다. 이점에 착안하여, 본 논문에서는 CPM모델을 제안하였다. CPM 모델은 아날로그 컴퓨팅, 디지털 컴퓨팅, 휴먼 컴퓨팅 등 세 가지 연산 메커니즘을 포괄할 수 있도록 설계되었다. 본 논문에서는, CPM 모델이 갖는 이러한 속성이 유비쿼터스 공간에서의 정보 연결 목적에 부합됨을 보였다.

• 한국ITS학회 논문지
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• 제11권4호
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• pp.63-69
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• 2012

본 논문에서는 용량성 지문센서의 회색조 이미지를 얻기 위한 새로운 회로를 제안하고 있다. 기존의 회로는 회색조 이미지를 얻기 위해 많은 칩 면적을 차지하는 DAC를 적용하거나 전력소모가 많고 전역 클럭을 적용하는 비휘발성 메모리에 적용되는 승압회로를 픽셀별로 적용하였다. 개선된 전하분할 방식의 용량성 지문센서 감지회로는 뉴런모스(vMOS) 기반의 DLC(down literal circuit) 회로와 단순화된 아날로그 MUX(multiplexor)를 적용하였다. 설계된 감지회로는 0.3V, $0.35{\mu}m$ CMOS공정을 적용하여 동작을 검증하였다. 제안된 회로는 기존의 비교기와 주변회로를 필요로하지 않으므로 단위 픽셀의 레이아웃 면적을 줄이고 이미지의 해상도를 향상 시킬 수 있다.