• Journal of Electrical Engineering and Technology
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• 제10권4호
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• pp.1655-1666
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• 2015

This paper proposes a new approach of Field Programmable Gate Array (FPGA) controlled digital implementation of shunt active power filter (SAPF) under steady state and dynamic operations. Typical implementations of SAPF uses microprocessor and digital signal processor (DSP) but it limited for complex algorithm structure, absence of feedback loop delays and their cost can be exceed the benefit they bring. In this paper, the hardware resources of an FPGA are configured and implemented in order to overcome conventional microcontroller or digital signal processor implementations. This proposed FPGA digital implementation scheme has very less execution time and boosts the overall performance of the system. The FPGA controller integrates the entire control algorithm of an SAPF, including synchronous reference frame transformation, phase locked loop, low pass filter and inverter current controller etc. All these required algorithms are implemented with a single all-on chip FPGA module which provides freedom to reconfigure for any other applications. The entire algorithm is coded, processed and simulated using Xilinx 12.1 ISE suite to estimate the advantages of the proposed system. The coded algorithm is also defused on a single all-on-chip Xilinx Spartan 3A DSP-XC3SD1800 laboratory prototype and experimental results thus obtained match with simulated counterparts under the dynamic state and steady state operating conditions.

• 전기전자학회논문지
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• 제17권3호
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• pp.248-253
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• 2013

주파수 판별기는 주파수를 디지털 비트 신호로 변환해주는 회로로서 변조기, 동기화 회로 등에 쓰인다. 본 논문에서는 여러 종류의 일차, 이차 주파수 판별기의 구조를 모델링하고 양자화 잡음 성능을 분석하며, 새로운 구조의 델타-시그마 주파수 판별기 구조를 제안한다. 이론적 분석과 유도된 수식으로부터 출구 잡음을 구하고 모의실험으로 타당성을 검증하였다. 제안된 주파수 판별기는 전 디지털 회로로서 전 디지털 위상 잠금 루프의 궤환 경로에 적용될 수 있다.

• 조명전기설비학회논문지
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• 제28권12호
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• pp.65-73
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• 2014

In this paper, the detection scheme of the voltage variation using a two difference voltage is proposed. The conventional sag detector is from a single-phase digital phase-locked loop (DPLL) that is based on a d-q transformation using an all-pass filter (APF). The APF generates a virtual q-axis voltage component with $90^{\circ}$ phase delay but the APF cannot generate the virtual q-axis voltage depending on the phase of the grid voltage. To overcome the problem, q-axis voltage component is generated from difference between the current and previous value of d-axis voltage component in the stationary reference frame. However, the difference voltage around the zero crossing is not enough to detect the voltage sag. Therefore, the new detection scheme using the two difference voltage which can detect the sag around the zero crossing voltage is proposed.

• Journal of Electrical Engineering and Technology
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• 제6권5호
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• pp.658-665
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• 2011

In the present paper, a novel fast peak detector for single- or three-phase unsymmetrical voltage sags is proposed. The proposed detector is modified from a single-phase digital phase-locked loop based on a d-q transformation using an all-pass filter (APF). APF generates a virtual phase with $90^{\circ}$ phase delay. However, this virtual phase cannot reflect a sudden change of the grid voltage in the moment of voltage sag, which causes a peak value to be significantly distorted and to settle down slowly. Specifically, the settling time of the peak value is too long when voltage sag occurs around a zero crossing, such as phase $0^{\circ}$ and $180^{\circ}$. This paper describes the operating principle of the APF problem and proposes a modified all-pass filter (MAPF) to mitigate the inherent APF problem. In addition, a new fast peak detector using MAPF is proposed. The proposed detector is able to calculate a peak value within 0.5 ms, even when voltage sag occurs around zero crossing. The proposed fast peak detector is compared with the conventional detector using APF. Results show that the proposed detector has faster detection time in the whole phase range. Furthermore, the proposed fast peak detector can be effectively applied to unsymmetrical three-phase voltage sags. Simulation and experimental results verify the advantages of the proposed detector and MAPF.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(II)
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• pp.874-877
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• 1987

In this paper a DPLL circuit realizable by digital IC's is propose and the principles of general DPLL are described. An all Digital phase locked loop is designed, analyzed, and tested. In particular, the approach of invoking Gaussian assumption on the decision variable and based on S.O.Rices theory is used. As a performance of the above PLL detector operating on low data rate FSK is given and demonsrtated to be FSK reception.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권4호
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• pp.272-281
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• 2013

This paper presents low power frequency shift keying (FSK) transmitter using all digital PLL (ADPLL) for smart utility network (SUN). In order to operate at low-power and to integrate a small die area, the ADPLL is adopted in transmitter. The phase noise of the ADPLL is improved by using a fine resolution time to digital converter (TDC) and digitally controlled oscillator (DCO). The FSK transmitter is implemented in $0.18{\mu}m$ 1-poly 6-metal CMOS technology. The die area of the transmitter including ADPLL is $3.5mm^2$. The power consumption of the ADPLL is 12.43 mW. And, the power consumptions of the transmitter are 35.36 mW and 65.57 mW when the output power levels are -1.6 dBm and +12 dBm, respectively. Both of them are supplied by 1.8 V voltage source. The frequency resolution of the TDC is 2.7 ps. The effective DCO frequency resolution with the differential MOS varactor and sigma-delta modulator is 2.5 Hz. The phase noise of the ADPLL output at 1.8 GHz is -121.17 dBc/Hz with a 1 MHz offset.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 하계학술대회 논문집 B
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• pp.1477-1479
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• 2004

Increasing numbers of photovoltaic arrays are being connected to the power utility through the power conditioning systems (PCS). This has raised potential problems of network protection. If, due to the action of the PCS, the local network voltage and frequency remain within regulatory limits when the utility is disconnected, then islanding is said to occur. In this paper, the representative methods to prevent the islanding are described and a PSIM-based model and analysis of the reactive power variation (RPV) method are presented. A novel phase detector using the all-pass filter and digital phase locked loop (DPLL) is proposed especially for the single-phase PCS. Finally, this paper provides the simulation and experimental results with a single-phase 3kW prototype PCS. Islanding test method of IEEE Std. 929-2000 was performed for verification.

• ETRI Journal
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• 제29권4호
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• pp.421-429
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• 2007

This paper presents a direct-conversion CMOS transceiver for fully digital DS-UWB systems. The transceiver includes all of the radio building blocks, such as a T/R switch, a low noise amplifier, an I/Q demodulator, a low pass filter, a variable gain amplifier as a receiver, the same receiver blocks as a transmitter including a phase-locked loop (PLL), and a voltage controlled oscillator (VCO). A single-ended-to-differential converter is implemented in the down-conversion mixer and a differential-to-single-ended converter is implemented in the driver amplifier stage. The chip is fabricated on a 9.0 $mm^2$ die using standard 0.18 ${\mu}m$ CMOS technology and a 64-pin MicroLead Frame package. Experimental results show the total current consumption is 143 mA including the PLL and VCO. The chip has a 3.5 dB receiver gain flatness at the 660 MHz bandwidth. These results indicate that the architecture and circuits are adaptable to the implementation of a wideband, low-power, and high-speed wireless personal area network.

• Journal of Power Electronics
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• 제18권6호
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• pp.1830-1843
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• 2018

In this paper, the generation of a reference current and voltage signal based on a Kalman filter is offered for a 3-phase 4wire UPQC (Unified Power Quality Conditioner). The performance of the UPQC is improved with source voltages that are distorted due to harmonic components. Despite harmonic and frequency variations, the Kalman filter is capable enough to determine the amplitude and the phase angle of load currents and source voltages. The calculation of the first state is sufficient to identify the fundamental components of the current, voltage and angle. Therefore, the Kalman state estimator is fast and simple. A Kalman based control strategy is proposed and implemented for a UPQC in a distribution system. The performance of the proposed control strategy is assessed for all possible source conditions with varying nonlinear and linear loads. The functioning of the proposed control algorithm with a UPQC is scrutinized and validated through simulations employing MATLAB/Simulink software. Using a FPGA SPATRAN 3A DSP board, the proposed algorithm is developed and implemented. A small-scale laboratory prototype is built to verify the simulation results. The stated control scheme for the UPQC reduces the following issues, voltage sags, voltage swells, harmonic distortions (voltage and current), unbalanced supply voltage and unbalanced power factor under dynamic and steady-state operating conditions.

• 대한전자공학회논문지SD
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• 제48권2호
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• pp.7-13
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• 2011

본 논문에서는 디지털 위상고정루프(All-digital PLL)를 구성하는 핵심 블록인 시간-디지털 변환기(Time-to-Digital Converter)를 제안하고 구현하였다. 본 연구에서는 게이티드 링 오실레이터 시간-디지털 변환기(GRO-TDC)의 기본 구조에 버니어 지연단(VDL)을 이용하여 다중 위상을 얻음으로써 보다 높은 해상도를 얻을 수 있는 구조를 제안하였다. 게이티드 링 오실레이터(GRO)는 총 7개의 지연셀을 사용하였고, 버니어 지연단(VDL) 3단을 이용하여 총 21개의 다중 위상을 사용하여 시간-디지털 변환기(TDC)를 설계하였다. 제안한 회로는 $0.13{\mu}m$ 1P-6M CMOS 공정을 사용하여 설계 및 구현하였다. 측정결과, 제안한 시간-디지털 변환기(TDC)의 최대 입력 주파수는 100MHz이고, 해상도는 26ps로 측정되었으며, 출력은 8-비트이며, 검출이 가능한 최대 위상 차이는 5ns의 위상 차이까지 검출이 가능하였다. 전력 소비는 측정된 Enable 신호의 크기에 따라 최소 8.4mW에서 최대 12.7mW로 측정되었다.