Journal of IKEEE (전기전자학회논문지)

Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
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Architecture and Noise Analysis of Frequency Discriminators

주파수 판별기 구조 및 잡음 성능 분석

  • Park, Sungkyung (Dept. of Electronics Engineering, Pusan National University)
  • Received : 2013.03.04
  • Accepted : 2013.03.15
  • Published : 2013.09.30
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Abstract

Frequency detector is a circuit that converts the frequency to a digital representation and finds its application in various fields such as modulator and synchronization circuitry. In this paper, a couple of first-order and second-order frequency discriminator structures are modeled and analyzed with their quantization noise sources. Also a delta-sigma frequency detector architecture is proposed. Through theoretical analysis and derived equations, the output noise is obtained, which is validated by simulation. The proposed all-digital frequency discriminator may be applied in the feedback path of the all-digital phase-locked loop.

주파수 판별기는 주파수를 디지털 비트 신호로 변환해주는 회로로서 변조기, 동기화 회로 등에 쓰인다. 본 논문에서는 여러 종류의 일차, 이차 주파수 판별기의 구조를 모델링하고 양자화 잡음 성능을 분석하며, 새로운 구조의 델타-시그마 주파수 판별기 구조를 제안한다. 이론적 분석과 유도된 수식으로부터 출구 잡음을 구하고 모의실험으로 타당성을 검증하였다. 제안된 주파수 판별기는 전 디지털 회로로서 전 디지털 위상 잠금 루프의 궤환 경로에 적용될 수 있다.

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References

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