JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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A 12 mW ADPLL Based G/FSK Transmitter for Smart Utility Network in 0.18 ㎛ CMOS

  • Park, Hyung-Gu (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Kim, Hongjin (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Lee, Dong-Soo (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Yu, Chang-Zhi (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Ku, Hyunchul (Konkuk University) ;
  • Lee, Kang-Yoon (College of Information and Communication Engineering, Sungkyunkwan University)
  • Received : 2012.12.13
  • Accepted : 2013.03.12
  • Published : 2013.08.31
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Abstract

This paper presents low power frequency shift keying (FSK) transmitter using all digital PLL (ADPLL) for smart utility network (SUN). In order to operate at low-power and to integrate a small die area, the ADPLL is adopted in transmitter. The phase noise of the ADPLL is improved by using a fine resolution time to digital converter (TDC) and digitally controlled oscillator (DCO). The FSK transmitter is implemented in $0.18{\mu}m$ 1-poly 6-metal CMOS technology. The die area of the transmitter including ADPLL is $3.5mm^2$. The power consumption of the ADPLL is 12.43 mW. And, the power consumptions of the transmitter are 35.36 mW and 65.57 mW when the output power levels are -1.6 dBm and +12 dBm, respectively. Both of them are supplied by 1.8 V voltage source. The frequency resolution of the TDC is 2.7 ps. The effective DCO frequency resolution with the differential MOS varactor and sigma-delta modulator is 2.5 Hz. The phase noise of the ADPLL output at 1.8 GHz is -121.17 dBc/Hz with a 1 MHz offset.

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References

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