• ETRI Journal
• /
• v.26 no.6
• /
• pp.583-588
• /
• 2004

In this paper we investigate the effect of a shield metal line inserted between adjacent bit lines on the refresh time and noise margin in a planar DRAM cell. The DRAM cell consists of an access transistor, which is biased to 2.5V during operation, and an NMOS capacitor having the capacitance of 10fF per unit cell and a cell size of $3.63{\mu}m^2$. We designed a 1Mb DRAM with an open bit-line structure. It appears that the refresh time is increased from 4.5 ms to 12 ms when the shield metal line is inserted. Also, it appears that no failure occurs when $V_{cc}$ is increased from 2.2 V to 3 V during a bump up test, while it fails at 2.8 V without a shield metal line. Raphael simulation reveals that the coupling noise between adjacent bit lines is reduced to 1/24 when a shield metal line is inserted, while total capacitance per bit line is increased only by 10%.

• Journal of IKEEE
• /
• v.17 no.3
• /
• pp.260-266
• /
• 2013

The open bit line is vulnerable to noise compared to the folded bit line when read/write for the DRAM. According to the increasing DRAM densities, the core circuit operating conditions is exacerbated by the noise when it comes to the open bit line 6F2(F : Feature Size) structure. In this paper, the interference effects were analyzed by the data patterns between the bit line by experiments. It was beyond the scope of existing research. 68nm Tech. 1Gb DDR2, Advan Tester used in the experiments. The noise effects appears the degrade of internal operation margin of DRAM. This paper investigates sense amplifier power line splits by experiments. The noise can be improved by 0.2ns(1.3%)~1.9ns(12.7%), when the sense amplifier power lines split. It was simulated by 68nm Technology 1Gb DDR2 modeling.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.6
• /
• pp.17-24
• /
• 2004

This paper describes a novel bit line structure to minimize coupling noise induced by coupling capacitance between bit lines. In DRAMs coupling capacitance is inherently present bit lines. As in submicron process the bit line space gets narrower. bit line coupling capacitance increases and this increased coupling capacitance sharply raises cross-talk noise. In this paper using different layers of metal for adjacent bit lines has been tested to reduces cross-talk noise and a novel bit line structure capable of reducing capacitance is introduced and verified.

• Journal of Sensor Science and Technology
• /
• v.23 no.5
• /
• pp.349-355
• /
• 2014

In this paper, we developed a new method to transmit multiple visible light channels in time division mode using the AC power line frequency in order to prevent the crosstalk between adjacent optical signals. Synchronizing pulses are generated from the 220 V power line, and one pulse period is subdivided into several time slots for visible light channels. Each channel transmits data in a predefined time slot without interfering adjacent channels. In experiments, synchronizing pulses with a repetition rate of 240 Hz were generated from the 60 Hz power line, and three VLC channels with a bit rate of 9.6 kbps transmitted data independently using the time slots between synchronizing pulses. This configuration is very useful in constructing time division VLC networks for multiple sensors.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.1 no.2
• /
• pp.125-131
• /
• 2001

When the program voltage is applied to a word line, a part of the boosted channel charge in inhibited bit lines is lost due to the coupling between the string select line (SSL) and the adjacent word line. This phenomenon causes the program disturbance in the cells connected to the inhibited bit lines. This program disturbance becomes more serious, as the word line pitch is decreased. To reduce the word line coupling, the rising edge of the word-line voltage waveform was changed from a pulse step into a ramp waveform with a controlled slope. The word-line ramping circuit was composed of a timer, a decoder, a 8 b D/A converter, a comparator, and a high voltage switch pump (HVSP). The ramping voltage was generated by using a stepping waveform. The rising time and the stepping number of the word-line voltage for programming were set to $\mutextrm{m}-$ and 8, respectively,. The ramping circuit was used in a 512Mb NAND flash memory fabricated with a $0.15-\mutextrm{m}$ CMOS technology, reducing the SSL coupling voltage from 1.4V into a value below 0.4V.

• Proceedings of the IEEK Conference
• /
• 2000.11b
• /
• pp.55-58
• /
• 2000

This paper describes a single transistor type ferroelectric field effect transistor (1T FeFET) memory celt scheme which can select one unit memory cell and program/read it. To solve the selection problem of 1T FeEET memory cell array, the row direction common well is electrically isolated from different adjacent row direction column. So, we can control voltage of common well line. By applying bias voltage to Gate and Well, respectively, we can implant IT FeEET memory cell scheme which no interface problem and can bit operation. The results of HSPICE simulations showed the successful operations of the proposed cell scheme.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.13 no.4
• /
• pp.402-409
• /
• 2013

An innovative application of voltage-contrast (VC) inspection allowed inline detection of NMOS leakage in dense SRAM cells is presented. Cell sizes of SRAM are continual to do the shrinkage with bit density promotion as semiconductor technology advanced, but the resulting challenges include not only development of smaller-scale devices, but also intra-devices isolation. The NMOS leakage caused by the underneath n+/P-well shorted to the adjacent PMOS/N-well was inspected by the proposed electron-beam (e-beam) scan in which VC images were compared during the in-line process step of post contact tungsten (W) CMP (Chemical Mechanical Planarization) instead of end-of-line electrical test, which has a long response time. A series of experiments based on the mechanism for improving the intra-well isolation was performed and verified by the inline VC inspection. An optimal process-integration condition involved to the tradeoff between the implant dosage and photo CD was carried out.

• Journal of Korean Tunnelling and Underground Space Association
• /
• v.5 no.2
• /
• pp.135-146
• /
• 2003

This paper presents the effect of ground vibration induced by vibrohammer and RCD on adjancent subway tunnel performance using FDM program. Firstly, the stability criteria for structures near vibration source were proposed according to existing data, then peak particle velocity around tunnel was estimated based on detailed information of vibrohammer and existing formula for dynamic loads through numerical analysis. The peak particle velocity induced by RCD bit rotation was also estimated using surveyed data and formula. Consequently, displacement and stress responses were obtained at crown, shoulder and spring line and compared with the criteria to check stability of tunnel.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.8 no.6
• /
• pp.460-469
• /
• 2015

This study's aim is for reducing big data transfer time of IoT healthcare devices by modulating digital bits into Manchester code including zero-voltage idle as information for secondary compressed binary cluster's compartment after two step compression of compressing binary data into primary and secondary binary compressed clusters for each binary clusters having compression benefit of 1 bit or 2 bits. Also this study proposed that as department information of compressed binary clusters, inserting idle signal into Manchester code will have benefit of reducing transfer time in case of compressing binary cluster into secondary compressed binary cluster by 2 bits, because in spite of cost of 1 clock idle, another 1 bit benefit can play a role of reducing 1 clock transfer time. Idle signal is also never consecutive because the signal is for compartment information between two adjacent secondary compressed binary cluster. Voltage transition on basic rule of Manchester code is remaining while inserting idle signal, so DC balance can be guaranteed. This study's simulation result said that even compressed binary data by another compression algorithms could be transferred faster by as much as about 12.6 percents if using this method.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.22 no.6
• /
• pp.1210-1230
• /
• 1997

In this paper, we suggest an architecture of DS/CDMA tranceiver composed of one pilot channel used as reference and multiple traffic channels. The pilot channel-an unmodulated PN code-is used as the reference signal for synchronization of PN code and data demondulation. The coherent demodulation architecture is also exploited for the reverse link as well as for the forward link. Here are the characteristics of the suggested DS/CDMA system. First, we suggest an interlaced quadrature spreading(IQS) method. In this method, the PN coe for I-phase 1st channel is used for Q-phase 2nd channels and the PN code for Q-phase 1st channel is used for I-phase 2nd channel, and so on-which is quite different from the eisting spreading schemes of DS/CDMA systems, such as IS-95 digital CDMA cellular or W-CDMA for PCS. By doing IQS spreading, we can drastically reduce the zero crossing rate of the RF signals. Second, we introduce an adaptive threshold setting for the synchronization of PN code, an initial acquistion method that uses a single PN code generator and reduces the acquistion time by a half compared the existing ones, and exploit the state machines to reduce the reacquistion time Third, various kinds of functions, such as automatic frequency control(AFC), automatic level control(ALC), bit-error-rate(BER) estimator, and spectral shaping for reducing the adjacent channel interference, are introduced to improve the system performance. Fourth, we designed and implemented the DS/CDMA MODEM to be used for variable transmission rate applications-from 16Kbps to 1.024Mbps. We developed and confirmed the DS/CDMA MODEM architecture through mathematical analysis and various kind of simulations. The ASIC design was done using VHDL coding and synthesis. To cope with several different kinds of applications, we developed transmitter and receiver ASICs separately. While a single transmitter or receiver ASC contains three channels (one for the pilot and the others for the traffic channels), by combining several transmitter ASICs, we can expand the number of channels up to 64. The ASICs are now under use for implementing a line-of-sight (LOS) radio equipment.