• 한국산업융합학회 논문집
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• 제3권2호
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• pp.167-178
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• 2000

Software RAID(Redundant Arrays of Inexpensive Disks) is defined as a storage system that provides capabilities of hardware RAID, and guarantees high reliability as well as high performance. In this paper, we propose an enhanced disk scheduling algorithm and a scheme to guarantee reliability of data. We also design and implement software RAID by utilizing these mechanism to develop a storage system for multimedia applications. Because the proposed algorithm improves a defect of traditional GSS algorithm that disk I/O requests arc served in a fixed order, it minimizes buffer consumption and reduces the number of deadline miss through service group exchange. Software RAID also alleviates data copy overhead during disk services by sharing kernel memory. Even though the implemented software RAID uses the parity approach to guarantee reliability of data, it adopts different data allocation scheme. Therefore, we reduce disk accesses in logical XOR operations to compute the new parity data on all write operations. In the performance evaluation experiments, we found that if we apply the proposed schemes to implement the Software RAID, it can be used as a storage system for small-sized video-on-demand servers.

• 한국콘텐츠학회:학술대회논문집
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• 한국콘텐츠학회 2003년도 춘계종합학술대회논문집
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• pp.223-226
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• 2003

DDoS(Distributed Denial of Service) 공격으로부터 시스템 자원을 보호하기 위한 최선의 방법은 공격자에 의해 전송되어진 패킷의 경로를 역추적하여 공격자의 근원지로부터 근본적인 DDoS 공격을 차단하는 것이다. 기존의 패킷 마킹 기법은 IP 식 별자필드를 마킹필드로 사용함으로써 ICMP의 사용이 불가능하고, 라우터 토를 이용한 역추적기법은 라우터의 수가 증가할 경우 마킹필드의 크기가 증가하는 문제점을 가지고 있다. 본 논문에서 제안한 역추적 기법은 IP 헤더의 옵션필드를 마킹필드로 사용하여 ICMP를 사용을 가능하게 하였고, 라우터 IP주소를 태R 연산하여 얻어진 값을 마크정보로 사용함으로써 라우터 수의 증가에도 마크정보의 크기가 변하지 않도록 제안하였다.

• Progress in Superconductivity
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• 제6권1호
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• pp.7-12
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• 2004

Due to the very fast switching speed of Josephson junctions, superconductive digital circuit has been a very good candidate fur future electronic devices. High-speed and Low-power microprocessor can be developed with Josephson junctions. As a part of an effort to develop superconductive microprocessor, we have designed an RSFQ 4-bit ALU (Arithmetic Logic Unit) in a pipelined structure. To make the circuit work faster, we used a forward clocking scheme. This required a careful design of timing between clock and data pulses in ALU. The RSFQ 1-bit block of ALU used in this work consisted of three DC current driven SFQ switches and a half-adder. We successfully tested the half adder cell at clock frequency up to 20 GHz. The switches were commutating output ports of the half adder to produce AND, OR, XOR, or ADD functions. For a high-speed test, we attached switches at the input ports to control the high-speed input data by low-frequency pattern generators. The output in this measurement was an eye-diagram. Using this setup, 1-bit block of ALU was successfully tested up to 40 GHz. An RSFQ 4-bit ALU was fabricated and tested. The circuit worked at 5 GHz. The circuit size of the 4-bit ALU was 3 mm ${\times}$ 1.5 mm, fitting in a 5 mm ${\times}$ 5 mm chip.

• 전자공학회논문지C
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• 제35C권2호
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• pp.56-64
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• 1998

Multi-layered perceptrons that are a nonlinear neural network model, have been widely used for various applications mainly thanks to good function approximation capability for nonlinear fuctions. However, for digital hardware implementation of the multi-layere perceptrons, the quantization scheme using "look-up tables (LUTs)" is commonly employed to handle nonlinear signmoid activation functions in the neworks, and thus requires large amount of storage to prevent unacceptable quantization errors. This paper is concerned with a new effective methodology for digital hardware implementation of multi-layered perceptrons, and proposes a "piecewise affine approximation" method in which input domain is divided into (small number of) sub-intervals and nonlinear sigmoid function is linearly approximated within each sub-interval. Using the proposed method, we develop an expression and an error backpropagation type learning algorithm for a multi-layered perceptron, and compare the performance with the quantization method through Monte Carlo simulations on XOR problems. Simulation results show that, in terms of learning convergece, the proposed method with a small number of sub-intervals significantly outperforms the quantization method with a very large storage requirement. We expect from these results that the proposed method can be utilized in digital system implementation to significantly reduce the storage requirement, quantization error, and learning time of the quantization method.quantization method.

• 대한전자공학회논문지SD
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• 제43권10호
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• pp.104-110
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• 2006

오늘날 시스템 온 칩 테스트에 있어서 많은 양의 테스트 데이터, 시간 및 전력 소모는 매우 중요한 문제이다. 이러한 문제들을 해결하기 위해서 본 논문은 새로운 테스트 데이터 압축 기술을 제안한다. 우선, 테스트 큐브 집합에 있는 돈 캐어 비트에 저전력 테스트를 위한 비트할당을 한다. 그리고, 비트할당이 된 저전력 테스트 데이터의 압축효율을 높이기 위해 이웃 비트 배타적 논리합 변환을 사용하여 변환한다. 최종적으로, 변환된 테스트 데이터는 효과적으로 압축됨으로써 테스트 장비의 저장공간과 테스트 데이터 인가시간을 줄일 수 있게 된다.

• 한국지능시스템학회논문지
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• 제5권3호
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• pp.83-91
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• 1995

본 연구에서는 종래에 학습법으로 널리 이용되고 있는 역전파학습법의 문제점으로 지적되어 온 학습에 많은 시간이 걸리는 점과 국소적 최적해에 해가 수렴하여 오차가 충분히 작게 되지 않는 등의 문제점을 해결하기 위해, Hu에 의해 고안된 random tabu 탐색법을 이용하여 신경회로망의 연결강도를 최적화하는 학습알고리즘을 새로이 제안하였다. 그리고 이 방법을 배타적 논리합 문제에 적용하여 기존의 역전파학습법과 학습상수 $, $에 tabu탐색법을 이용한 결과와 비교 검토하여 본 방법이 국소적 최적해에 수렴하지 않고 수렴정도를 개선할 수 있음을 확인하였다.

• 한국초전도ㆍ저온공학회논문지
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• 제7권1호
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• pp.9-12
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• 2005

We have constructed an RSFQ 4-bit Arithmetic Logic Unit (ALU) in a pipelined structure. An ALU is a core element of a computer processor that performs arithmetic and logic operation on the operands in computer instruction words. We have simulated the circuit by using Josephson circuit simulation tools. We used simulation tools of XIC, $WRspice^{TM}$, and Julia. To make the circuit work faster, we used a forward clocking scheme. This required a careful design of timing between clock and data pulses in ALU. The RSFQ 1-bit block of ALU used in constructing the 4-bit ALU was consisted of three DC current driven SFQ switches and a half-adder. By commutating output ports of the half adder, we could produce AND, OR, XOR, or ADD functions. The circuit size of the 4-bit ALU when fabricated was 3 mm x 1.5 mm, fitting in a 5 mm x 5mm chip. The fabricated 4-bit ALU operated correctly at 5 GHz clock frequency. The chip was tested at the liquid-helium temperature.

• 한국초전도ㆍ저온공학회논문지
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• 제7권1호
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• pp.21-24
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• 2005

The problem of fluctuation-induced digital errors in a rapid single flux quantum (RSFQ) circuit has been very important issue. So in this experiment, we calculated error rate of RSFQ switch in superconductiyity ALU, The RSFQ switch should have a very low error rate in the optimal bias. We prepared two circuits Placed in parallel. One was a 10 Josephson transmission lines (JTLs) connected in series, and the other was the same circuit but with an RSFQ switch placed in the middle of the 10 JTLs. We used a splitter to feed the same input signal to the both circuits. The outputs of the two circuits were compared with an RSFQ XOR to measure the error rate of the RSFQ switch. By using a computerized bit error rate test setup, we measured the bit error rate of 2.18$\times$$10^{12}$ when the bias to the RSFQ switch was 0.398mh that was quite off from the optimum bias of 0.6mA.

• 대한임베디드공학회논문지
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• 제14권6호
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• pp.313-319
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• 2019

Finite field operations have played an important role in error correcting codes and cryptosystems. Recently, the necessity of efficient computation processing is increasing for security in cyber physics systems. Therefore, efficient implementation of finite field arithmetics is more urgently needed. These operations include addition, multiplication, division and inversion. Addition is very simple and can be implemented with XOR operation. The others are somewhat more complicated than addition. Among these operations, multiplication is the most important, since time-consuming operations, such as exponentiation, division, and computing multiplicative inverse, can be performed through iterative multiplications. In this paper, we propose a multiplexer based parallel computation algorithm that performs Montgomery multiplication over finite field using redundant basis. Then we propose an efficient multiplexer based semi-systolic multiplier over finite field using redundant basis. The proposed multiplier has less area-time (AT) complexity than related multipliers. In detail, the AT complexity of the proposed multiplier is improved by approximately 19% and 65% compared to the multipliers of Kim-Han and Choi-Lee, respectively. Therefore, our multiplier is suitable for VLSI implementation and can be easily applied as the basic building block for various applications.

• Progress in Superconductivity
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• 제6권2호
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• pp.104-107
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• 2005

We have developed and tested an RSFQ 4-bit Arithmetic Logic Unit (ALU) based on half adder cells and de switches. ALU is a core element of a computer processor that performs arithmetic and logic operations on the operands in computer instruction words. The designed ALU had limited operation functions of OR, AND, XOR, and ADD. It had a pipeline structure. We have simulated the circuit by using Josephson circuit simulation tools in order to reduce the timing problem, and confirmed the correct operation of the designed ALU. We used simulation tools of $XIC^{TM},\;WRspice^{TM}$, and Julia. The fabricated 4-bit ALU circuit had a size of $\3000{\ cal}um{\times}1500{\cal}$, and the chip size was $5{\cal} mm{\times}5{\cal}mm$. The test speeds were 1000 kHz and 5 GHz. For high-speed test, we used an eye-diagram technique. Our 4-bit ALU operated correctly up to 5 GHz clock frequency. The chip was tested at the liquid-helium temperature.