IEMEK Journal of Embedded Systems and Applications (대한임베디드공학회논문지)

Institute of Embedded Engineering of Korea (대한임베디드공학회)
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Multiplexer-Based Finite Field Multiplier Using Redundant Basis

여분 기저를 이용한 멀티플렉서 기반의 유한체 곱셈기

  • Received : 2019.09.03
  • Accepted : 2019.11.07
  • Published : 2019.12.31
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Abstract

Finite field operations have played an important role in error correcting codes and cryptosystems. Recently, the necessity of efficient computation processing is increasing for security in cyber physics systems. Therefore, efficient implementation of finite field arithmetics is more urgently needed. These operations include addition, multiplication, division and inversion. Addition is very simple and can be implemented with XOR operation. The others are somewhat more complicated than addition. Among these operations, multiplication is the most important, since time-consuming operations, such as exponentiation, division, and computing multiplicative inverse, can be performed through iterative multiplications. In this paper, we propose a multiplexer based parallel computation algorithm that performs Montgomery multiplication over finite field using redundant basis. Then we propose an efficient multiplexer based semi-systolic multiplier over finite field using redundant basis. The proposed multiplier has less area-time (AT) complexity than related multipliers. In detail, the AT complexity of the proposed multiplier is improved by approximately 19% and 65% compared to the multipliers of Kim-Han and Choi-Lee, respectively. Therefore, our multiplier is suitable for VLSI implementation and can be easily applied as the basic building block for various applications.

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References

  1. R.E. Blahut, Theory and Practice of Error Control Codes, Reading, MA, Addison-Wesley, 1983.
  2. A.J. Menezes, P.C. van Oorschot, S.A. Vanstone, Handbook of Applied Cryptography, Boca Raton, FL, CRC Press, 1996.
  3. N. Kobliz, "Elliptic Curve Cryptography," Journal of Math. Computation, Vol. 48, No. 177, pp. 203-209, 1987. https://doi.org/10.1090/S0025-5718-1987-0866109-5
  4. S.Y. Park, W.J. Choi, B.H. Chung, J.N. Kim, J.M. Kim, "The Study on the Cyber Security Requirements of Cyber-Physical Systems for Cyber Security Frameworks," IEMEK J. Embed. Sys. Appl., Vol. 7, No. 5, pp. 255-265, 2012 (in Korean). https://doi.org/10.14372/IEMEK.2012.7.5.255
  5. M. Wolf, D. Serpanos, "Safety and Security in Cyber-Physical Systems and Internet-of-Things Systems," Proceedings of the IEEE, Vol. 106, No. 1, pp. 9-20, 2018. https://doi.org/10.1109/JPROC.2017.2781198
  6. P. Montgomery, "Modular Multiplication Without Trial division," Journal of Mathematics of Computation, Vol. 44, No. 170, pp. 519-521, 1985. https://doi.org/10.1090/S0025-5718-1985-0777282-X
  7. C.K. Koc, T. Acar, "Montgomery multiplication in GF ($2^k$)," Journal of Designs Codes and Cryptography, Vol. 14, No. 1, pp. 57-69, 1998. https://doi.org/10.1023/A:1008208521515
  8. C.Y. Lee, J.S. Horng, I.C. Jou, E.H. Lu, "Low-complexity Bit-parallel systolic Montgomery Multipliers for Special Classes of GF ($2^m$)," Journal of IEEE Transactions on Computers, Vol. 54, No. 9, pp. 1061-1070, 2005. https://doi.org/10.1109/TC.2005.147
  9. C.W. Chiou, C.Y. Lee, A.W. Deng, J.M. Lin, "Concurrent Error Detection in Montgomery Multiplication Over GF ($2^m$)," Journal of Institute of Electronics, Information and Communication Engineers Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. 89, No. 2, pp. 566-574, 2006
  10. A. Hariri A. Reyhani-Masoleh: "Bit-serial and Bit-parallel Montgomery Multiplication and Squaring over GF ($2^m$)," Journal of IEEE Transactions on Computers, Vol. 58, No. 10, pp. 1332-1345, 2009. https://doi.org/10.1109/TC.2009.70
  11. K.W. Kim, J.C. Jeon, "A Semi-systolic Montgomery Multiplier over GF($2^m$)," Journal of Institute of Electronics, Information and Communication Engineers Electronics Express, Vol. 12, No. 21, pp. 20150769, 2015.
  12. W.T. Huang, C.H. Chang, C.W. Chiou, F.H. Chou, "Concurrent Error Detection and Correction in a Polynomial Basis Multiplier over GF ($2^m$)," Journal of Institution of Engineering and Technology Information Security, Vol. 4, No. 3, pp. 111-124, 2010.
  13. K.W. Kim, S.H. Kim, "A Low Latency Semi-systolic Multiplier over GF (2m)," Journal of Institute of Electronics, Information and Communication Engineers Electronics Express, Vol. 10, No. 13, pp. 20130354, 2013.
  14. K.W. Kim, S.C. Han, "Low Latency Systolic Multiplier over GF (2m) Using Irrdeucible AOP," IEMEK J. Embed. Sys. Appl., Vol. 11, No. 4, pp. 227-233, 2016 (in Korean). https://doi.org/10.14372/IEMEK.2016.11.4.227
  15. S.H. Choi, K.J. Lee, "Low Complexity Semi-systolic Multiplication Architecture over GF (2m)," Journal of Institute of Electronics, Information and Communication Engineers Electronics Express, Vol. 11, No. 20, pp. 20140713, 2014.
  16. T.W. Kim, K.W. Kim, "Low-latency Montgomery AB2 Multiplier Using Redundant Representation over GF (2m)," IEMEK J. Embed. Sys. Appl., Vol. 12, No. 1, pp. 11-18, 2017 (in Korean). https://doi.org/10.14372/IEMEK.2017.12.1.11
  17. G. Drolet, "A New Representation of Elements of Finite Fields Yielding Small Complexity Arithmetic Circuits," Journal of IEEE Transactions on Computers, Vol. 47, No. 9, pp. 938-946, 1998. https://doi.org/10.1109/12.713313
  18. H. Wu, M.A. Hasan, I.F. Blake, S. Gao, "Finite Field Multiplier Using Redundant Representation," Journal of IEEE Transactions on Computers, Vol. 51, No. 11, pp. 1306-1316, 2002. https://doi.org/10.1109/TC.2002.1047755
  19. K.Z. Pekmestzi, "Multiplexer-based Array Multipliers," Journal of IEEE Transactions on Computers, Vol. 48, No. 1, pp. 15-23, 1999. https://doi.org/10.1109/12.743408
  20. R.J. Baker, H.W. Li, D.E. Boyce, CMOS Circuit, Design, Layout, and Simulation, Wiley-IEEE Press, 1998.
  21. STMicroelectronics. Avaliable on : http://www.st.com