• Journal of electromagnetic engineering and science
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• v.9 no.3
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• pp.152-158
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• 2009

We have developed a novel digital feedback predistortion(DFBPD) linearization based on RF feedback PD for the wide bandwidth modulated signals. The wideband PD operation is carried out by combining the DFBPD and memory lookup table(LUT). To experimentally demonstrate the linearization performance of the proposed PD technique for wideband signal, a class-AB amplifier using an LDMOSFET MRF6S23140 with 140-W peak envelope power is employed at 2.345 GHz. For a forward-link 2FA wideband code-division multiple-access signal with 10 MHz carrier spacing, the proposed DFBPD with memory LUT delivers the adjacent channel leakage ratio at an 10 MHz offset of -56.8 dBc, while those of the amplifier with and without DFBPD are -43.2 dBc and -41.9 dBc, respectively, at an average output power of 40 dBm. The experimental result shows that the new DFBPD with memory LUT provides a good linearization performance for the signal with wide bandwidth.

• ETRI Journal
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• v.36 no.6
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• pp.924-930
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• 2014

This paper presents a $0.13{\mu}m$ CMOS 3-level envelope delta-sigma modulation (EDSM) RF signal generator, which synthesizes a 2.6 GHz-centered fully symmetrical 3-level EDSM signal for high-efficiency power amplifier architectures. It consists of an I-Q phase modulator, a Class B wideband buffer, an up-conversion mixer, a D2S, and a Class AB wideband drive amplifier. To preserve fast phase transition in the 3-state envelope level, the wideband buffer has an RLC load and the driver amplifier uses a second-order BPF as its load to provide enough bandwidth. To achieve an accurate 3-state envelope level in the up-mixer output, the LO bias level is optimized. The I-Q phase modulator adopts a modified quadrature passive mixer topology and mitigates the I-Q crosstalk problem using a 50% duty cycle in LO clocks. The fabricated chip provides an average output power of -1.5 dBm and an error vector magnitude (EVM) of 3.89% for 3GPP LTE 64 QAM input signals with a channel bandwidth of 10/20 MHz, as well as consuming 60 mW for both channels from a 1.2 V/2.5 V supply voltage.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.1
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• pp.37-43
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• 2001

In this paper, we designed a linear power amplifier considering its delay characteristics fur wideband operation. The power amplifier has the gain of 37 dB and is designed in 3-stage typ with 1W output power. The error amplifier has the gain of 55 dB and is designed in 4-stage typ. And directional coupler and power divider are designed. Vector modulator is used to adjust magnitude and phase of signal. A linear power amplifier, that is assembled with each modules, is designed considering the delay characteristics for 2.11~2.2 GHz. Its C/I3 ratio has been improved by B5 dB for bandwidth of 30 MHz.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.1
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• pp.13-20
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• 2015

Existing LDMOS power amplifier that used class-AB and doherty system shows 55% of efficiency in 60MHz narrow band. Because RRH has been applied to power amplifier at base station. It is required that over 100MHz expanded band and more than 60% high efficiency power amplifier. In this paper we designed class-J power amplifier using LDMOS FET which has over 60% high efficiency characteristic in 200MHz. The output matching circuit of designed class-J power amplifier has been optimized to contain pure reactance at second harmonic load and has low quality factor Q. As a measurement result of the amplifier, when we input continuous wave signal, we checked 62~70% of power added efficiency(PAE) in 2.06~2.2GHz including WCDMA frequency as a 10W class-J power amplifier.

• Journal of electromagnetic engineering and science
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• v.2 no.2
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• pp.112-116
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• 2002

In this paper, the active integrated antenna(AIA) using a wideband printed dipole antenna and a balanced amplifier is designed and fabricated. The proposed active printed dipole antenna has characteristics of easy matching, wide bandwidth and higher output power To feed balanced signal to printed dipole, a Wilkinson power divider and delay lines are used. The measured result shows that, at 6 GHz center frequency, the impedance bandwidth is 22 % (VSWR < 2), 3 dB gain bandwidth is 28 %, the maximum gain is 14.77 dBi, and output power at P1 dB point is 23 dBm.

• Proceedings of the KIEE Conference
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• 2007.10a
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• pp.193-194
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• 2007

This paper presents the design of a power amplifier for full-band UWB application systems using a CMOS 0..18um technology. A wideband RLC filter and a multilevel RLC matching scheme are utilized to achieve the wideband input/output matching. Both the cascade and cascode stage are used to increase the gain and to achieve gain flatness. Simulation results show that the designed amplifier provides a power gain greater than 10 dB throughout the UWB full-band(3.1-10.6GHz) and an input P1dB of -1.2dBm at 6.9GHz. It consumes 35.8mW from a 1.8V supply.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.7
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• pp.620-626
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• 2015

In this paper, a 2~6 GHz wideband GaN power amplifier MMIC is designed and fabricated using a second-order all-pass filter for input impedance matching and an LC parallel resonant circuit for minimizing an output reactance component of the transistor. The second-order all-pass filter used for wideband lossy matching is modified in an asymmetric configuration to compensate the effect of channel resistance of the GaN transistor. The power amplifier MMIC chip that is fabricated using a $0.25{\mu}m$ GaN HEMT foundry process of Win Semiconductors, Corp. is $2.6mm{\times}1.3mm$ and shows a flat linear gain of about 13 dB and input return loss of larger than 10 dB. Under a saturated power mode, it also shows output power of 38.6~39.8 dBm and a power-added efficiency of 31.3~43.4 % in 2 to 6 GHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.12
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• pp.1205-1214
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• 2013

Recently spaceborne SAR systems are increasing image resolution and frequency. As a high quality image resolution, the wider bandwidth is required and a wideband signal generator with RF component is very complicated and RF impairments of device is increased. Therefore, it is very important to improve performance by reducing these errors. In this study, the transmission signal of the wideband signal generator is applied to the phase noise, IQ imbalance, ripple gain, nonlinear model of high power amplifier. And we define possible structures of wideband signal generator and measure the PSLR and ISLR for the performance assesment. Also, we extract error of the amplitude and phase from the waveform and use a quadratic polynomial curve fitting and examine the performance change due to nonlinear device. Finally, we apply a high power amplifier predistortion method for non-linear error compensation. And we confirm that distortion in the output of the amplifier by intermodulation component is decreased by 15 dB.

• ETRI Journal
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• v.29 no.5
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• pp.670-672
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• 2007

An ultra-wideband low-noise amplifier is proposed with operation up to 8.2 GHz. The amplifier is fabricated with a 0.18-${\mu}m$ CMOS process and adopts a two-stage cascode architecture and a simplified Chebyshev filter for high gain, wide band, input-impedance matching, and low noise. The gain of 19.2 dB and minimum noise figure of 3.3 dB are measured over 3.4 to 8.2 GHz while consuming 17.3 mW of power. The Proposed UWB LNA achieves a measured power-gain bandwidth product of 399.4 GHz.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.833-836
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• 1999

In this paper, a wideband MMIC LNA was designed using low Q matching network. Gains of 9.8~12.2 ㏈, and noise figures of 1.7~2.1 ㏈ were obtained from the fabricated wideband MMIC LNA in the frequency ranges of 1.5~2.5㎓. And maximum output power of 10.83 ㏈m were obtained at the center frequency of 2 ㎓. The chip size of the fabricated wideband MMIC low noise amplifier is 1.4 mm$\times$1.4 mm.