• Title/Summary/Keyword: Wide locking range

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Analog Delay Locked Loop with Wide Locking Range

  • Yoo, Changsik
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.1 no.3
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    • pp.193-196
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    • 2001
  • For wide locking range, an analog delay locked loop (DLL) was designed with the selective phase inversion scheme and the variable number of delay elements. The number of delay elements was determined adaptively depending on the clock cycle time. During the analog fine locking stage, a self-initializing 3-state phase detector was used to avoid the initial state problem associated with the conventional 3-state phase detector. With these schemes, the locking range of analog DLL was increased by four times compared to the conventional scheme according to the simulation results.

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A Study on the Wide-band Fast-Locking Digital PLL Design (광대역 고속 디지털 PLL의 설계에 대한 연구)

  • Ahn, Tae-Won
    • 전자공학회논문지 IE
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    • v.46 no.1
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    • pp.1-6
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    • 2009
  • This paper presents the digital PLL architecture and design for improving the frequency detection range and locking time for wide-band frequency synthesizer applications. In this research, a wide-range digital logic quadricorrelator is used for wide-band and fast frequency detector and sigma-delta modulator with 2-bit up-down counter is adopted for DCO control. The proposed digital PLL reduces the phase noise from quantization effect and is suitable for implementation of wide-band fast-locking as well as low power features, which is in high demand for mobile multimedia applications.

A Wide Range PLL for 64X CD-ROMs & l0X DVD-ROMs (64배속 CD-ROM 및 10배속 DVD-ROM용 광대역 위상 고정 루프)

  • 진우강;이재신;최동명;이건상;김석기
    • Proceedings of the IEEK Conference
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    • 1999.11a
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    • pp.340-343
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    • 1999
  • In this paper, we propose a wide range PLL(Phase Locked Loop) for 64X CD-ROMs & l0X DVD-ROMs. The frequency locking range of the Proposed PLL is 75MHz~370MHz. To reduce jitters caused by large VCO gain and supply voltage noise, a new V-I converter and a differential delay cell are used in 3-stage ring VCO, respectively. The new V-I converter has a 0.6V ~ 2.5V wide input range. In addition, we propose a new charge pump which has perfect current matching characteristics for the sourcing/sinking current. This new charge pump improves the locking time and the locking range of the PLL. This Chip is implemented in 0.25${\mu}{\textrm}{m}$ CMOS process. It consumes 55㎽ in worst case with a single 2.5V power supply.

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A Wide-range Tunable Wavelength-stabilization Technique for Semiconductor Lasers

  • Chen, Han;Qiao, Qinliang;Min, Jing;He, Cong;Zhang, Yuanyuan
    • Current Optics and Photonics
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    • v.5 no.4
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    • pp.384-390
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    • 2021
  • This paper presents a wide-range tunable wavelength-locking technology based on optoelectronic oscillation (OEO) loops for optical fiber sensors and microwave photonics applications, explains the theoretical fundamentals of the design, and demonstrates a method for locking the relative wavelength differences between a leader semiconductor laser and its follower lasers. The input of the OEO loop in the proposed scheme (the relative wavelength difference) determines the radio-frequency (RF) signal frequency of the oscillation output, which is quantized into an injection current signal for feedback to control the wavelength drift of follower lasers so that they follow the wavelength change of the leader laser. The results from a 10-hour continuous experiment in a field environment show that the wavelength-locking accuracy reached ±0.38 GHz with an Allan deviation of 6.1 pm over 2 hours, and the wavelength jitter between the leader and follower lasers was suppressed within 0.01 nm, even though the test equipment was not isolated from vibrations and the temperature was not controlled. Moreover, the tunable range of wavelength locking was maintained from 10 to 17 nm for nonideal electrical devices with limited bandwidth.

A Dual Charge Pump PLL-based Clock Generator with Power Down Schemes for Low Power Systems (저 전력 시스템을 위한 파워다운 구조를 가지는 이중 전하 펌프 PLL 기반 클록 발생기)

  • Ha, Jong-Chan;Hwang, Tae-Jin;Wee, Jae-Kyung
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.11
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    • pp.9-16
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    • 2005
  • This paper proposes a programmable PLL (phase locked loop) based clock generator supporting a wide-range-frequency input and output for high performance and low power SoC with multiple clock frequencies domains. The propose system reduces the locking time and obtains a wide range operation frequency by using a dual-charge pumps scheme. For low power operation of a chip, the locking processing circuits of the proposed PLL doesn't be working in the standby mode but the locking data are retained by the DAC. Also, a tracking ADC is designed for the fast relocking operation after stand-by mode exit. The programmable output frequency selection's circuit are designed for supporting a optimized DFS operation according to job tasks. The proposed PLL-based clock system has a relock time range of $0.85{\mu}sec{\sim}1.3{\mu}sec$($24\~26$cycle) with 2.3V power supply, which is fabricated on $0.35{\mu}m$ CMOS Process. At power-down mode, PLL power saves more than $95\%$ of locking mode. Also, the PLL using programmable divider has a wide locking range ($81MHz\~556MHz$) for various clock domains on a multiple IPs system.

Development of Curved Beam Element with Shear Effect (전단효과를 고려한 곡선보 요소 개발)

  • 이석순;구정서;최진민
    • Transactions of the Korean Society of Mechanical Engineers
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    • v.17 no.10
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    • pp.2535-2542
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    • 1993
  • Two-noded curved beam elements, CMLC (field-consistent membrane and linear curvature) and IMLC(field-inconsistent membrane and linear curvature) are developed on the basis of Timoshenko's beam theory and curvilinear coordinate. The curved beam element is developed by the separation of the radial deflection into the bending deflection. In the CMLC element, field-consistent axial strain interpolation is adapted for removing the membrane locking. The CMLC element shows the rapid and stable convergence on the wide range of curved beam radius to thickness. The field-consistent axial strain and the separation of radial deformation produces the most efficient linear element possible.

A Wide-Range Dual-Loop DLL using VCDL with Transmission Gate Inverters (TG Inverter VCDL을 사용한 광대역 Dual-Loop DLL)

  • Lee, Seok-Ho;Kim, Sam-Dong;Hwang, In-Seok
    • Proceedings of the IEEK Conference
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    • 2005.11a
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    • pp.829-832
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    • 2005
  • This paper describes a wide-range dual-loop Delay Locked Loop (DLL) using Voltage Controlled Delay Line (VCDL) based on Transmission Gate(TG) inverters. One loop is used when the minimum VCDL delay is greater than a half of $T_{REF}$, the reference clock period. The other loop is initiated when the minimum delay is less than $0.5{\times}T_{REF}$. The proposed VCDL improves the dynamic operation range of a DLL. The DLL with a VCDL of 10 TG inverters provides a lock range from 70MHz to 700MHz when designed using $0.18{\mu}m$ CMOS technology with 1.8 supply voltage. The DLL consumes 11.5mW for locking operation with a 700MHz reference clock. The proposed DLL can be used for high-speed memory devices and processors, communication systems, high-performance display interfaces, etc.

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Voltage Controlled Injection-Locked Oscillator Design at 2.4 GHz Band for Wideband Applications (광대역 응용을 위한 2.4 GHz 대역 전압 제어 주입 동기 발진기 설계)

  • Yoon, Won-Sang;Lee, Hun-Sung;Lee, Hee-Jong;Pyo, Seong-Min;Kim, Young-Sik;Han, Sang-Min
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.22 no.3
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    • pp.292-298
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    • 2011
  • In this paper, a voltage controlled injection-locked oscillator(VC-ILO) is proposed for wideband applications. From the control of the free-running frequency by a varactor diode, the wide frequency locking range can be obtained for low-level injected signals. The proposed VC-ILO is implemented on an FR-4 substrate with a thickness of 0.8 mm. The free-running frequencies of the oscillator is 2.39~2.52 GHz at the control voltage of 0~5 V. While the frequency locking range of over 50 MHz is presented for -10 dBm injected signal level at a fixed frequency, the locking range of over 90 MHz can be achieved for -30 dBm by controlling the free-running frequency.

Design of a 40 GHz CMOS Phase-Locked Loop Frequency Synthesizer Using Wide-Band Injection-Locked Frequency Divider (광대역 주입동기식 주파수 분주기 기반 40 GHz CMOS PLL 주파수 합성기 설계)

  • Nam, Woongtae;Sohn, Jihoon;Shin, Hyunchol
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.27 no.8
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    • pp.717-724
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    • 2016
  • This paper presents design of a 40 GHz CMOS PLL frequency synthesizer for a 60 GHz sliding-IF RF transceiver. For stable locking over a wide bandwith for a injection-locked frequency divider, an inductive-peaking technique is employed so that it ensures the PLL can safely lock across the very wide tuning range of the VCO. Also, Injection-locked type LC-buffer with low-phase noise and low-power consumption is added in between the VCO and ILFD so that it can block any undesirable interaction and performance degradation between VCO and ILFD. The PLL is designed in 65 nm CMOS precess. It covers from 37.9 to 45.3 GHz of the output frequency. and its power consumption is 74 mA from 1.2 V power supply.