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http://dx.doi.org/10.5515/KJKIEES.2016.27.8.717

Design of a 40 GHz CMOS Phase-Locked Loop Frequency Synthesizer Using Wide-Band Injection-Locked Frequency Divider  

Nam, Woongtae (Department of Wireless Communications Engineering, Kwangwoon University)
Sohn, Jihoon (Department of Wireless Communications Engineering, Kwangwoon University)
Shin, Hyunchol (Department of Wireless Communications Engineering, Kwangwoon University)
Publication Information
The Journal of Korean Institute of Electromagnetic Engineering and Science / v.27, no.8, 2016 , pp. 717-724 More about this Journal
Abstract
This paper presents design of a 40 GHz CMOS PLL frequency synthesizer for a 60 GHz sliding-IF RF transceiver. For stable locking over a wide bandwith for a injection-locked frequency divider, an inductive-peaking technique is employed so that it ensures the PLL can safely lock across the very wide tuning range of the VCO. Also, Injection-locked type LC-buffer with low-phase noise and low-power consumption is added in between the VCO and ILFD so that it can block any undesirable interaction and performance degradation between VCO and ILFD. The PLL is designed in 65 nm CMOS precess. It covers from 37.9 to 45.3 GHz of the output frequency. and its power consumption is 74 mA from 1.2 V power supply.
Keywords
mm-Wave; PLL; Frequency Synthesizer; Wide Locking Range ILFD; Inductive-Peaking Technique;
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