• Journal of the Microelectronics and Packaging Society
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• v.27 no.1
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• pp.67-73
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• 2020

In this paper, we used FEM technique to perform warpage and von Mises stress analysis on PCB according to the cavity structures of embedded PCB for FCCSP and the types of prepreg material. One-half substrate model and static analysis are applied to the FEM. According to the analysis results of the warpage, as the gap between the cavity and the chip increased, warpage increased and warpage increased when prepreg material with higher modularity and thermal expansion coefficient was applied. The analysis results of the von Mises stress show that the effect of the gap between the cavity and the chip varies depending on prepreg material. In other words, when material whose coefficient of thermal expansion is significantly higher than that of core material, the stress increased as the gap between the cavity and the chip increased. When the prepreg with the coefficient of thermal expansion lower than the core material is applied, the result of stress is opposite. These results indicate that from a reliability perspective, there is a correlation between the structure of the cavity where embedded chips are loaded and prepreg material.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.3
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• pp.63-69
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• 2013

The warpage of a bottom package of Package on Package(PoP) where a chip was mounted to a substrate by flip chip process was compared to that of a bottom package for which a chip was bonded to a substrate using die attach film(DAF). At the solder reflow temperature of $260^{\circ}C$, the packages processed with flip chip bonding and DAF bonding exhibited warpages of $57{\mu}m$ and $-102{\mu}m$, respectively. At the temperature range between room temperature and $260^{\circ}C$, the packages processed with flip chip bonding and DAF bonding exhibited warpage values ranging from $-27{\mu}m$ to $60{\mu}m$ and from $-50{\mu}m$ to $-15{\mu}m$, respectively.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.4
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• pp.59-66
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• 2018

In this paper, we analyzed the usefulness of single-structured printed circuit board (PCB) modeling by using numerical analysis to model the PCB structure applied to a package for semiconductor purposes and applying modeling assuming a single structure. PCBs with circuit layer of 3rd and 4th were used for analysis. In addition, measurements were made on actual products to obtain material characteristics of a single structure PCB. The analysis results showed that if the PCB was modeled in a single structure compared to a multi-layered structure, the warpage analysis results resulting from modeling the PCB structure would increase and there would be a significant difference. In addition, as the circuit layer of the PCB increased, the mechanical properties of the PCB, the elastic coefficient and inertia moment of the PCB increased, decreasing the package's warpage.

• Journal of the Microelectronics and Packaging Society
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• v.28 no.4
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• pp.31-39
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• 2021

In this paper, warpage analysis that separates PCB for PoP (Package on Package) into unit and substrate using FEM (Finite Element Method), analysis of the effect of layer thickness on warpage, and SN (Signal-to-Noise) ratio by Taguchi method was carried. According to the analysis result, the contribution of the circuit layer on warpage was very high in the unit PCB, and the contribution of the outer layer was particularly high. On the other hand, the substrate PCB had a high influence of the circuit layer on warpage, but it was relatively low compared to the unit PCB, and the influence of the solder resist was rather increased. Therefore, considering the unit PCB and the substrate PCB at the same time, it is desirable to design the PCB for PoP layer-by-layer structure so that the outer and inner circuit layers are thick, the top solder resist is thin, and the thickness of the bottom solder resist is between 5 ㎛ and 25 ㎛.

• Journal of the Semiconductor & Display Technology
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• v.22 no.4
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• pp.124-130
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• 2023

Recently, fan out wafer level packaging, which enables high integration, miniaturization, and low cost, is being rapidly applied in the semiconductor industry. In particular, FOWLP is attracting attention in the mobile and Internet of Things fields, and is recognized as a core technology that will lead to technological advancements such as 5G, self-driving cars, and artificial intelligence in the future. However, as chip density and package size within the package increase, FOWLP warpage is emerging as a major problem. These problems have a direct impact on the reliability and electrical performance of semiconductor products, and in particular, cause defects such as vacuum leakage in the manufacturing process or lack of focus in the photolithography process, so technical demands for solving them are increasing. In this paper, warpage simulation according to the thickness of FOWLP material was performed using finite element analysis. The thickness range was based on the history of similar packages, and as a factor causing warpage, the curing temperature of the materials undergoing the curing process was applied and the difference in deformation due to the difference in thermal expansion coefficient between materials was used. At this time, the stacking order was reflected to reproduce warpage behavior similar to reality. After performing finite element analysis, the influence of each variable on causing warpage was defined, and based on this, it was confirmed that warpage was controlled as intended through design modifications.

• Design & Manufacturing
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• v.6 no.1
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• pp.67-72
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• 2012

Most of the plastics products have been manufactured by injection molding. Molding trouble in injection-molded parts is caused by changing a molding product and molding process condition, etc. In this study, warpage in the injection molded part have been studied. Specimens are rectangular flat shape with and without ribs. Non-crystalline resins (ABS+GF30%, PC+GF30%) and crystalline resins (PP+GF30%, PA66+GF30%) were used for material. Flat shape ribs showed higher warpage than flat shape without rib by 10 to 41%. the specimens with ribs that are located parallel to flow direction has higher warpage than the specimens with rib that are located perpendicular to flow direction by 11 to 50%. crystalline resins have higher warpage than non-crystalline resins by 22 to 78%. Warpage decreases as packing time increases as injection temperature increases.

• Journal of the Microelectronics and Packaging Society
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• v.23 no.1
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• pp.17-22
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• 2016

Flexible organic light-emitting diode (OLED) devices consist of multi-stacked thin films or layers comprising organic and inorganic materials. Due to thermal coefficient mismatch of the multi-layer films, warpage of the flexible OLED is generated during high temperature process of each layer. This warpage will create the critical issues for next production process, consequently lowering the production yield and reliability of the flexible OLED. In this study, we investigate the warpage behavior of the flexible OLED for each bonding process step of the multi-layer films using the experimental and numerical analysis. It is found that the polarizer film and barrier film show significant impact on warpage of flexible OLED, while the impact of the OCA film on warpage is negligible. The material that has the most dominant impact on the warpage is a plastic cover. In order to minimize the warpage of the flexible OLED, we estimate the optimal material properties of the plastic cover using design of experiment. It is found that the warpage of the flexible OLED is reduced to less than 1 mm using a cover plastic of optimized properties which are the elastic modulus of 4.2 GPa and thermal expansion coefficient of $20ppm/^{\circ}C$.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.4
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• pp.49-60
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• 2010

Semiconductor packages are increasingly moving toward miniaturization, lighter and high performance. Futhermore, packages become thinner. Thin packages will generate serious reliability problems such as warpage, crack and other failures. Reliability problems are mainly caused by the CTE mismatch of various package materials. Therefore, proper selection of the package materials and geometrical optimization is very important for controlling the warpage and the stress of the package. In this study, we investigated the characteristics of the warpage and the stress of several packages currently used in mobile devices such as CABGA, fcSCP, SCSP, and MCP. Warpage and stress distribution are analyzed by the finite element simulation. Key material properties which affect the warpage of package are investigated such as the elastic moduli, CTEs of EMC molding and the substrate. Geometrical effects are also investigated including the thickness or size of EMC molding, silicon die and substrate. The simulation results indicate that the most influential factors on warpage are EMC molding thickness, CTE of EMC, elastic modulus of the substrate. Simulation results show that warpage is the largest for SCSP. In order to reduce the warpage, DOE optimization is performed, and the optimization results show that warpage of SCSP becomes $10{\mu}m$.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.1
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• pp.41-45
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• 2018

As the size of semiconductor chip shrinks, the electronic industry has been paying close attention to fan-out wafer level packaging (FO-WLP) as an emerging solution to accommodate high input and output density. FO-WLP also has several advantages, such as thin thickness and good thermal resistance, compared to conventional packaging technologies. However, one major challenge in current FO-WLP manufacturing process is to control wafer warpage, caused by the difference of coefficient of thermal expansion and Young's modulus among the materials. Wafer warpage induces misalignment of chips and interconnects, which eventually reduces product quality and reliability in high volume manufacturing. In order to control wafer warpage, it is necessary to understand the effect of material properties and design parameters, such as chip size, chip to mold ratio, and carrier thickness, during packaging processes. This paper focuses on the effects of thickness of chip and molding compound on 12" wafer warpage after PMC of EMC using finite element analysis. As a result, the largest warpage was observed at specific thickness ratio of chip and EMC.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.3
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• pp.89-93
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• 2020

Complex warpage behavior of the electronic packages causes internal stress so many kinds of mechanical failure occur such as delamination or crack. Efforts to predict the warpage behavior accurately in order to prevent the decrease in yield have been approached from various aspects. For warpage prediction, silicon is generally treated as a homogeneous material, therefore it is described as showing no warpage behavior due to thermal loading. However, it was reported that warpage is actually caused by residual stress accumulated during grinding and polishing in order to make silicon wafer thinner, which make silicon wafer inhomogeneous through thickness direction. In this paper, warpage behavior of the single-side polished wafer at solder reflow temperature, the highest temperature in packaging processes, was measured using 3D digital image correlation (DIC) method. Mechanism was verified by measuring coefficient of thermal expansion (CTE) of both mirror-polished surface and rough surface.