• Journal of the Semiconductor & Display Technology
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• v.11 no.2
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• pp.33-38
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• 2012

The wafer positioning robot in the semiconductor industry is required to operate at high speed for the improvement of productivity. The residual vibration caused by the high speed of the wafer positioning robot, however, makes the life of the robot shorter and the cycle time longer. In this study, the input shaping and the path of the system are designed for the reduction of the residual vibration and the improvement of the cycle time. The followings are the process for the reduction and the improvement; 1) System modeling of the wafer positioning robot, 2) Verification of dynamic characteristics of the wafer positioning robot, 3) Input shaping plan using impulse response reiteration, 4) Simulation test using SIMULINK program, 5) Analysis of result.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.29 no.1 s.232
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• pp.96-106
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• 2005

An integrated single-wafer processing tool, composed of multiple single wafer processing modules, transfer robots, and load locks, has complex routing sequences, and often has critical post-processing residency constraints. Scheduling of these tools is an intricate problem, and testing schedulers with actual tools requires too much time and cost. The Single Wafer Processor (SWP) simulator presented in this paper is to validate an on-line scheduler, and evaluate performance of integrated single-wafer processing tools before the scheduler is actually deployed into real systems. The data transfer between the scheduler and the simulator is carried out with TCP/IP communication using messages and files. The developed simulator consists of six modules, i.e., GUI (Graphic User Interface), emulators, execution system, module managers, analyzer, and 3D animator. The overall framework is built using Microsoft Visual C++, and the animator is embodied using OpenGL API (Application Programming Interface).

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2005.11a
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• pp.559-563
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• 2005

The wafer positioning robot used in the semiconductor industry is required to operate at high speed for the improvement of productivity. However, the residual vibration produced by the high speed of the wafer positioning robot makes the life of the robot shorter and the cycle time longer. In this study, the input shaping and the path of the system are designed for the reduction of the residual vibration and the optimization of the cycle time. The followings are the process for the reduction and the optimization; 1)System modeling of wafer positioning robot, 2)Verification of dynamic characteristic of wafer positioning robot, 3)Input shaping plan using impulse response reiteration, 4)Simulation test using simulink, 6)Analysis of result.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.3
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• pp.196-203
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• 2004

A three-dimensional (3D) IC technology platform is presented for high-performance, low-cost heterogeneous integration of silicon ICs. The platform uses dielectric adhesive bonding of fully-processed wafer-to-wafer aligned ICs, followed by a three-step thinning process and copper damascene patterning to form inter-wafer interconnects. Daisy-chain inter-wafer via test structures and compatibility of the process steps with 130 nm CMOS sal devices and circuits indicate the viability of the process flow. Such 3D integration with through-die vias enables high functionality in intelligent wireless terminals, as vertical integration of processor, large memory, image sensors and RF/microwave transceivers can be achieved with silicon-based ICs (Si CMOS and/or SiGe BiCMOS). Two examples of such capability are highlighted: memory-intensive Si CMOS digital processors with large L2 caches and SiGe BiCMOS pipelined A/D converters. A comparison of wafer-level 3D integration 'lith system-on-a-chip (SoC) and system-in-a-package (SiP) implementations is presented.

• Journal of Korean Institute of Industrial Engineers
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• v.36 no.2
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• pp.125-137
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• 2010

This study focuses on the problem of scheduling wafer lots of several product families in the deposition workstation in a semiconductor wafer fabrication facility. There are multiple identical parallel machines in the deposition workstation, and two types of setups, record-dependent setup and family setup, may be required at the deposition machines. A record-dependent setup is needed to find optimal operational conditions for a wafer lot on a machine, and a family setup is needed between processings of different families. We suggest two-phase heuristic algorithms in which a priority-rule-based scheduling algorithm is used to generate an initial schedule in the first phase and the schedule is improved in the second phase. Results of computational tests on randomly generated test problems show that the suggested algorithms outperform a scheduling method used in a real manufacturing system in terms of the sum of weighted flowtimes of the wafer lots.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.42 no.5
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• pp.31-40
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• 2005

In this study, we study measurement of wafer processing throughput and sequence simulation of single wafer type for wafer cleaning equipments that were used for etching, cleaning and polishing of wafer. Based on finite state machine, simulation model was built with identification of robot's status according to scheduling algorithm. Moreover, through performance of simulation as above, throughput per hour of cleaning equipment was measured. By the simulation method that are proposed in this paper, we could measure the wafer throughput per hour according to recipe and robot motion speed, and find optimal recipe and moving sequence of robot that maximize the throughput.

• Journal of Korea Multimedia Society
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• v.13 no.3
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• pp.400-409
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• 2010

This paper presents a position error recognition system when the wafer is mounted in cleaning equipment among the wafer manufacturing processes. The proposed system is to enhance the performance in cost and reliability by preventing the wafer cleaning system from damaging by alerting it when it is put in correct position. The key algorithms are the calibration method between image acquired from camera and physical wafer, a infrared lighting and the design of the filter, and the extraction of wafer boundary and the position error recognition resulting from generation of circle based on least square method. The system is to install in-line process using high reliable and high accurate position recognition. The experimental results show that the performance is good in detecting errors within tolerance.

• Journal of Korea Foundry Society
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• v.33 no.2
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• pp.69-74
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• 2013

Silicon (Si) wafer was grown by using direct growth from Si melt and contaminations of wafer during the process were investigated. In our process, BN was coated inside of all graphite parts including crucible in system to prevent carbon contamination. In addition, coated BN layer enhance the wettability, which ensures the favorable shape of grown wafer by proper flow of Si melt in casting mold. As a result, polycrystalline silicon wafer with dimension of $156{\times}156$ mm and thickness of $300{\pm}20$ um was successively obtained. There were, however, severe contaminations such as BN and SiC on surface of the as-grown wafer. While BN powders were easily removed by brushing surface, SiC could not be eliminated. As a result of BN analysis, C source for SiC was from binder contained in BN slurry. Therefore, to eliminate those C sources, additional flushing process was carried out before Si was melted. By adding 3-times flushing processes, SiC was not detected on the surface of as-grown Si wafer. Polycrystalline Si wafer directly grown from Si melt in this study can be applied for the cost-effective Si solar cells.

• Korean Journal of Materials Research
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• v.25 no.1
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• pp.16-20
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• 2015

In this study, in order to improve the efficiency of n-type monocrystalline solar cells with an Alu-cell structure, we investigate the effect of the amount of Al paste in thin n-type monocrystalline wafers with thicknesses of $120{\mu}m$, $130{\mu}m$, $140{\mu}m$. Formation of the Al doped $p^+$ layer and wafer bowing occurred from the formation process of the Al back electrode was analyzed. Changing the amount of Al paste increased the thickness of the Al doped $p^+$ layer, and sheet resistivity decreased; however, wafer bowing increased due to the thermal expansion coefficient between the Al paste and the c-Si wafer. With the application of $5.34mg/cm^2$ of Al paste, wafer bowing in a thickness of $140{\mu}m$ reached a maximum of 2.9 mm and wafer bowing in a thickness of $120{\mu}m$ reached a maximum of 4 mm. The study's results suggest that when considering uniformity and thickness of an Al doped $p^+$ layer, sheet resistivity, and wafer bowing, the appropriate amount of Al paste for formation of the Al back electrode is $4.72mg/cm^2$ in a wafer with a thickness of $120{\mu}m$.

• Proceedings of the Korea Association of Crystal Growth Conference
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• 1996.06a
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• pp.88-138
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• 1996

Electronics grew up to the largest industry in the world supported by Si wafer. In near future, the Si wafer may use 300mm in diameter for economic requirement. This size wafer may use to produce large logic chip, 256Mbit DRAM, and other large complex and high density chip. Then, the quality including flatness and crustal characters may be required very high performance. And, their price should be reasonable and high quantity may be required. These requirements should be solve lot of hard problems of crystal growth, wafering mechanical processing and their cost problems. In this presentation, I may discuss following items.