• Journal of the Korean Operations Research and Management Science Society
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• v.18 no.1
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• pp.119-126
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• 1993

We study a manufacturing process that is quite common in semiconductor wafer fabrication of semiconductor chip production. A machine is used to process a job consisting of J wafers. Each job requires a setup, and the i$_{th}$ setup for a job is sucessful with probability P$_{i}$. The setup is prone to failure, which results in the loss of expensive wafers. Therefore, a tiral run is first conducted on a small batch. If the set up is successful, the test is passed and the balance of the job can be processed. If the setup is unsuccessful, the exposed wafers are lost to scrap and the mask is realigned. The process then repeats on the balance of the job. We call this as send-ahead policy and consider general policies in which the number of wafers that are sent shead depend on the cost of the raw wafer, the sequence of success probabilities, and the balance of the job. We model this process and determine the expected number of good wafers per job,the expected time to process a job, and the long run average throughput. An algorithm to minimize the cost per good wafer subject to a demand constraint is provided.d.d.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.32 no.2
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• pp.149-157
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• 2008

During CVD process of semiconductor wafer fabrication, maintaining the uniformity of temperature distribution at wafer top surface is one of the key factors affecting the quality of final products. Effect of contact conductance between wafer and hot plate on predicted temperature of wafer was investigated. The validity of opaque wafer assumption was also examined by comparing the predicted results with Discrete Ordinate solutions accounting for semitransparent radiative characteristics of silicon. As the contact conductance increases predicted wafer temperature increases and the differences between maximum and minimum temperatures within wafer and between wafer and hot plate top surface temperatures decrease. The opaque assumption always overpredicted the wafer temperature compared to semitransparent calculation. The influences of surrounding reactor inner wall temperature and hot plate configuration are then discussed.

• Journal of the Semiconductor & Display Technology
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• v.19 no.2
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• pp.77-81
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• 2020

Silicon wafer etching in micro electro mechanical systems (MEMS) fabrication is challenging to form 3-D structures. Well known Si-wet etch of silicon employs potassium hydroxide (KOH), tetramethylammonium hydroxide (TMAH) and sodium hydroxide (NaOH). However, the existing silicon wet etching process has a fatal disadvantage that etching of the back side of the wafer is hard to avoid. In this study, a wet etching bath for 150 mm wafers was designed to prevent back-side etching of silicon wafer, and we demonstrated the optimized process recipe to have anisotropic wet etching of silicon wafer without any damage on the backside. We also presented the design of wet bath for 300 mm wafer processing as a promising process development.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.43-49
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• 2013

We have studied on ozonate water cleaning mechanisms to apply in manufacturing process of 156 mm silicon wafer which is used in the solar cell fabrication. We have analyzed contamination sources on wafer surface which causes poor quality and performance of products in fabrication process, and examined cleaning process using ozonate water to eliminate it. Using this novel technology particles are removed over 94%, and remained organic materials are removed more over 45%.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.1101-1106
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• 2005

The purpose of this study was to develop a process management system to manage ingot fabrication and the quality of the ingot. The ingot is the first manufactured material of wafers. Operating data (trace parameters) were collected on-line but quality data (measurement parameters) were measured by sampling inspection. The quality parameters were applied to evaluate the quality. Thus, preprocessing was necessary to extract useful information from the quality data. First, statistical methods were employed for data generation, and then modeling was accomplished, using the generated data, to improve the performance of the models. The function of the models is to predict the quality corresponding to the control parameters. The dynamic polynomial neural network (DPNN) was used for data modeling that used the ingot fabrication data.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.874-877
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• 2001

SOI(Silicon-On-Insulator) technology is proposed as an alternative to bulk silicon for MEMS(Micro Electro Mechanical System) manufacturing. In this paper, we fabricated the SOI wafer with uniform active layer thickness by silicon direct bonding and mechanical polishing processes. Specially-designed electrostatic bonding system is introduced which is available for vacuum packaging and silicon-glass wafer bonding for SOG(Silicon On Glass) wafer. We demonstrated thermopile sensor and RF resonator using the SOI wafer, which has the merits of simple process and uniform membrane fabrication.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.8
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• pp.23-29
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• 2014

We have studied on ozonate water cleaning mechanisms to apply in manufacturing process of 156 mm silicon wafer which is used in the solar cell fabrication. We have analyzed contamination sources on wafer surface which causes poor quality and performance of products in fabrication process, and examined cleaning process using ozonate water to eliminate it. Contamination sources consist of remaining material like organic matter in slurry and detergent and particles in sawing wire. Using this novel technology it is possible for the solar cell wafer to clean with low cost, high performance, and eco-friendly.

• Journal of the Korean Vacuum Society
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• v.13 no.1
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• pp.1-8
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• 2004

The SOI wafer fabrication technique has been developed by using ion-cut process, based on proton implantation and wafer bonding techniques. It has been shown by TRIM simulation that 65 keV proton implantation is required for the standard SOI wafer (200 nm SOI, 400 nm BOX) fabrication. In order to investigate the optimum proton dose and primary annealing condition for wafer splitting, the surface morphologic change has been observed such as blistering and flaking. As a result, effective dose is found to be in the 6∼$9\times10^{16}$ $H^{+}/\textrm{cm}^2$ range, and the annealing at $550^{\circ}C$ for 30 minutes is expected to be optimum for wafer splitting. The depth distribution of implanted hydrogen has been experimentally confirmed by ERD and SIMS measurements. The microstructure evolution in the damaged layer was also studied by X-TEM analysis.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.261-264
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• 2007

We developed a non self-aligned poly-silicon TFTs fabrication process at two different temperatures on spin-coated polyimide layer above Si-wafer. After TFTs fabrication, the polyimide layer was mechanically released from the Si-wafer and the devices characteristics were compared. In addition self-heating and hot-carrier induced instabilities were analysed.

• Proceedings of the Korea Society for Simulation Conference
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• 2003.11a
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• pp.147-151
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• 2003

Yield enhancement in semiconductor fabrication is important. Even though DRAM yield loss may be attributed to many problems, the existence of defects on the wafer is one of the main causes. When the defects on the wafer form patterns, it is usually an indication for the identification of equipment problems or process variations. In this paper describes the techniques to automatically classify a failure pattern using a fail bit map.