• Journal of the Korean Society for Precision Engineering
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• v.19 no.2
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• pp.187-194
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• 2002

For the fine grinding process development of semiconductor monocrystalline silicon, wheel rotational speed, chuck rotational speed, feed rate and hysteresis force were controlled. Magic mirror system was used for grinding wheel pattern analysis. Curvature of wheel pattern was measured by fitting equation. The modeling of surface wheel pattern was related to wheel and chuck rotational speed. The calculated curvature of the model was well matched with the measured curvature. The statistical analysis indicated wheel and chuck rotational speed were significantly effective on.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.81-81
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• 2009

반도체 산업의 중심 소재인 실리콘(Si)은 사용 목적과 환경에 따라 물성적 한계가 표출되기 시작했다. 그래서 각각의 목적에 맞는 재료의 개발이 필요하다는 것을 인식하게 되었다. SiC wafer는 큰 band gap energy와 고온 안정성, 캐리어의 높은 드리프트 속도 그리고 p-n 접합이 용이하다. 또한 소재 자체가 화학적으로 안정하고 $500\sim600^{\circ}C$에서 소자 제조 시 고온공정이 가능하며, 실리콘이나 GaAs에 비해 고출력을 낼 수 있는 재료이다. 반도체 소자로 이용하기 위한 wafer 가공 공정에 있어 물리적 힘에 의한 stress를 많이 받아 wafer가 휘는 현상이 생긴다. 반도체 소자의 기본이 되는 wafer가 휨 현상을 일으키면 wafer 위에 소자가 올라갈 경우 소자의 불균일성 때문에 반도체의 물성에 나쁜 영향을 미치게 된다. 그래서 반도체 소자의 기본이 되는 wafer의 휨 현상 개선이 중요하다. 본 연구에서는 산화로에서 Ar 분위기에서 압력 760torr, 온도 $1100^{\circ}C$ 부근에서의 조건으로 진행을 하여 wafer의 Flatness Tester(FT-900, NIDEK) 장비로 SORI, BOW, GBIR 값의 변화에 초점을 맞추었다. SiC 단결정을 sawing후 가공 전 wafer를 열처리하여 가공을 진행하는 것과 열처리 하지 않은 wafer의 SORI, BOW, GBIR 값 비교, 그리고 lapping, grinding, polishing 등의 가공 진행 중간 중간에 열처리를 하여 진행하는 것과 가공 진행 중간 중간에 열처리를 하지 않고 진행한 wafer의 SORI, BOW, GBIR 값의 비교를 통해 wafer의 휨 현상 개성에 관해 알아본다.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 1998.03a
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• pp.196-202
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• 1998

Recently, developments in the frontier industry have brought a rapid increase in the use of brittle materials such as silicon wafer, ferrite, sintered carbide, MgO single crystal and die steel. Because of high hardness and brittleness the cracking and chipping are apt to generate in the grinding of brittle materials, but have replaced gradually the high precision grinding. In this study, the optimum system of in-process electrolytic dressing controlled by computer was developed for improving the defects, and could maintain the optimum dressing condition at all times. The control of in-process dressing was simplified using this system, was able to maintain a stable dressing current and was unrelated to the change of dressing condition according to the variation of gap and oxide layer. Therefore, the optimum in-process electrolytic dressing system was constructed and the analysis of grinding mechanism with this system was studied.

• Journal of the Korean Ceramic Society
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• v.40 no.8
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• pp.770-776
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• 2003

#140 mesh and #600 mesh wheels were adopted to grind (111) and (100) oriented single crystalline silicon wafer and the grinding induced change of the surface integrity was investigated. For this purpose, microroughness, residual stress and phase transformation were analyzed for the ground surface. Microroughness was analyzed using AFM (Atomic Force Microscope) and crystal structure was analyzed using micro-Raman spectroscopy. The residual stress and phase transformation were also analyzed after thermal annealing in the air. As a result, microroughness of (111) wafer was larger than that of (100) wafer after grinding. It was observed using Raman spectrum that the silicon was transformed from diamond cubic Si-I to Si-III(body centered tetragonal) or Si-XII(rhombohedral). Residual stress relaxation was also shown in cavities which were produced after grinding. The thermal annealing was effective for the recovery of the silicon phase to the original phase and the residual stress relaxation.

• Journal of the Korean Society for Precision Engineering
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• v.22 no.2
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• pp.46-52
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• 2005

The sapphire wafer was polished by the implementation of the surface machining technology based on nano-tribology, The removal process has been performed by grinding, lapping and chemical-mechanical polishing. For the chemical mechanical polishing process, the chemical reaction between the slurry and sapphire wafer was investigated in terms of the change of Zeta-potential between two materials. The Zeta-potential was -4.98 mV without the slurry in deionized water and was -37.05 mV for the slurry solution. By including the slurry into the deionized water the Zeta-potential -29.73 mV, indicating that the surface atoms of sapphire become more repulsive to be easy to separate. The average roughness of the polished surface of sapphire wafer was ranged to 1∼4$\AA$.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.2
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• pp.63-67
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• 2008

3D integration technology has been a major focus of the next generation of IC industries. In this study Si wafer ultra-thinning has been investigated especially for the effect of ultra-thinning on the silicon surface. Wafers were grinded down to $30{\mu}m\;or\;50{\mu}m$ thickness and then grinded only samples were compared with surface treated samples in terms of surface roughness, surface damages, and hardness. Dry polishing or wet etching treatment has been applied as a surface treatment. Surface treated samples definitely showed much less surface damages and better roughness. However, ultra-thinned Si samples have the almost same hardness as a bulk Si wafer.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.128-128
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• 2010

In this study, we investigated the evolution and reduction of the surface roughness during the high-speed chemical dry thinning process of Si wafers. The direct injection of NO gas into the reactor during the supply of F radicals from NF3 remote plasmas was very effective in increasing the Si thinning rate, due to the NO-induced enhancement of the surface reaction, but resulted in the significant roughening of the thinned Si surface. However, the direct addition of Ar and N2 gas, together with NO gas, decreased the root mean square (RMS) surface roughness of the thinned Si wafer significantly. The process regime for the increasing of the thinning rate and concomitant reduction of the surface roughness was extended at higher Ar gas flow rates. In this way, Si wafer thinning rate as high as $20\;{\mu}m/min$ and very smooth surface roughness was obtained and the mechanical damage of silicon wafer was effectively removed. We also measured die fracture strength of thinned Si wafer in order to understand the effect of chemical dry thinning on removal of mechanical damage generated during mechanical grinding. The die fracture strength of the thinned Si wafers was measured using 3-point bending test and compared. The results indicated that chemical dry thinning with reduced surface roughness and removal of mechanical damage increased the die fracture strength of the thinned Si wafer.

• Journal of the Korean Society for Precision Engineering
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• v.32 no.5
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• pp.463-470
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• 2015

Solar cell is typical representative of renewable green energy. Silicon wafer contributes about 66 percent to its cost structure. In its manufacturing, micro-cracks are often occurred due to manufacturing process such as wire sawing, grinding and cleaning. Their detection and classification are important to process feedback information. In this paper, a classification method of micro-cracks is proposed, based on the fusion of principal component analysis(PCA) and neural network. The proposed method shows that it gives higher results than single application of two methods, in terms of shape and size classification of micro-cracks.

• Korean Journal of Metals and Materials
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• v.49 no.9
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• pp.726-731
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• 2011

The present work shows how the flexural displacement-induced fracture strength of silicon devices, whose back surfaces have wafer grinding-induced scratch marks, depends on the crystallographic orientation. Experimental results indicate that silicon devices with scratch marks parallel to their lateral direction (i.e. reference axis in this work) are very susceptible to flexural fracture, as compared to devices with marks which deviated from the direction. The 3-point bending test shows that the fracture strength of silicon devices having marks which are oriented away from the reference axis is 2.6 times higher than that of devices with marks parallel to the axis. It was particularly interesting to see that silicon devices with identical preferred marks even reveal different fracture strengths, depending on whether the marks are involved in specific crystal planes such as {111} or {011}, called cleavage planes. This work demonstrates that silicon devices with the reference axis-aligned scratch marks not existing on such cleavage planes can have higher fracture strength approximately 20% higher than those existing on the planes.

• Journal of the Microelectronics and Packaging Society
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• v.6 no.4
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• pp.61-71
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• 1999

The recent trend toward higher frequencies, miniaturization and lower-cost in wireless communication equipment is demanding high density packaging technologies such flip chip interconnection and multichip module(MCM) as a substitute of conventional plastic package. With analyzing the recently reported research results of the RF flip chip, this paper presents the technical issues and advantages of RF flip chip and suggest the flip chip technologies suitable for the development stage. At first, most of RF flip chips are designed in a coplanar waveguide line instead of microstrip in order to achieve better electrical performance and to avoid the interaction with a substrate. Secondly, eliminating wafer back-side grinding, via formation, and back-side metallization enables the manufacturing cost to be reduced. Finally, the electrical performance of flip chip bonding is much better than that of plastic package and the flip chip interconnection is more suitable for Transmit/Receiver modules at higher frequency. However, the characterization of CPW designed RF flip chip must be thoroughly studied and the Au stud bump bonding shall be suggested at the earlier stage of RF flip chip development.