• 전기전자학회논문지
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• 제26권2호
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• pp.313-318
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• 2022

피드백 전압 감지 구조는 기존 외부 출력 캐패시터의 제거로 인한 오버슈트 및 언더슈트 현상을 완화하기 위해 제안된다. 기존의 LDO 레귤레이터는 전원 공급 전압의 불균형으로 인해 발생하는 오버슈트 및 언더슈트를 겪는다. 따라서 제안된 LDO는 기존 LDO의 피드백 경로만 유지하면서 새로운 제어 경로를 형성하기 위해 보다 개선된 과도 응답을 갖도록 설계되었다. 새로운 제어 경로는 출력 단계에서 발생하는 오버슈트 및 언더슈트 현상을 감지한다. 이에, 패스 소자의 게이트 노드의 전류를 충방전함으로써 패스 소자의 동작 속도가 향상된다. 피드백 전압 감지 구조가 있는 LDO 레귤레이터는 3.3~4.5V의 입력 전압 범위에서 작동하며 3V의 출력 전압에서 최대 200mA의 부하 전류를 가집니다. 시뮬레이션 결과에 따르면 부하전류가 200mA일 때 언더슈트 조건에서는 73mV, 오버슈트 조건에서는 61mV이다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권3호
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• pp.313-319
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• 2012

The power supply rejection (PSR) of low drop-out (LDO) voltage regulator is improved by employing an error amplifier (EA) which is configured so the power supply noise be cancelled at the output. The LDO regulator is implemented in a 0.13-${\mu}m$ standard CMOS technology. The external supply voltage level is 1.2-V and the output is 1.0-V while the load current can range from 0-mA to 50-mA. The power supply rejection is 46-dB, 49-dB, and 38-dB at DC, 2-MHz, and 10-MHz, respectively. The quiescent current consumption is 65-${\mu}A$.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2009년도 제40회 하계학술대회
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• pp.58_59
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• 2009

Generator excitation system, supplying the voltage to power system, is controlled by various manners as aspects of power system. Previously excitation systems mainly used AVR(Automatic Voltage Regulator) and FCR(Field Current Regulator) to control voltage, but nowadays the excitation systems have the tendency to adopt AQR(Automatic Reactive power Regulator) and APFR(Automatic Power Factor Regulator) to do it so as to get into step with diverse requirements of power system and high digital technology. This paper presents which operation methods is effective for the equipment, according to increase the unmanned power station thanks to automation technic.

• Journal of Electrical Engineering and Technology
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• 제6권6호
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• pp.817-823
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• 2011

This paper introduces an efficient voltage multiplier circuit for improved voltage gain and power efficiency of radio frequency identification (RFID) tags. The multiplier is fully integratable and takes advantage of both passive and active circuits to reduce the required input power while yielding the desired DC voltage. A six-stage voltage multiplier and an ultralow power voltage regulator are designed in a 0.13 ${\mu}m$ complementary metal-oxide semiconductor process for 2.45 GHz RFID applications. The minimum required input power for a 1.2 V supply voltage in the case of a 50 ${\Omega}$ antenna is -20.45 dBm. The efficiency is 15.95% for a 1 $M{\Omega}$ load. The regulator consumes 129 nW DC power and maintains the reference voltage in a 1.1% range with $V_{dd}$ varying from 0.8 to 2 V. The power supply noise rejection of the regulator is 42 dB near a 2.45 GHz frequency and performs better than -32 dB from 100 Hz to 10 GHz frequencies.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1996년도 하계학술대회 논문집 A
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• pp.385-387
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• 1996

A novel two stage soft-switching ac-to-dc convener with power factor correction is proposed. The proposed convener provides zero-voltage-switching (ZVS) condition to main switch of boost pre-regulator without auxiliary switch. Comparing to the conventional two stage approach(ZVS-PWM boost rectifier followed by off-line ZVS dc-dc step down converter), the proposed approach is simple and reducing EMI noise problem. A new simple DC-linked energy feedback circuit provides zero-voltage-switching condition to boost pre-regulator without imposing additional voltage and current stresses and loss of PWM capability. Operational principle, analysis, control of the proposed converter together with the simulation results of 1KW prototype are presented.

• Journal of electromagnetic engineering and science
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• 제14권4호
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• pp.376-381
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• 2014

We present a CMOS rail-to-rail class-AB amplifier using dynamic current biasing to improve the delay response of the error amplifier in a low-dropout (LDO) regulator, which is a building block for a wireless power transfer receiver. The response time of conventional error amplifiers deteriorates by slewing due to parasitic capacitance generated at the pass transistor of the LDO regulator. To enhance slewing, an error amplifier with dynamic current biasing was devised. The LDO regulator with the proposed error amplifier was fabricated in a $0.35-{\mu}m$ high-voltage BCDMOS process. We obtained an output voltage of 4 V with a range of input voltages between 4.7 V and 7 V and an output current of up to 212 mA. The settling time during line transient was measured as $9{\mu}s$ for an input variation of 4.7-6 V. In addition, an output capacitor of 100 pF was realized on chip integration.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제48권7호
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• pp.369-375
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• 1999

This paper presents the novel low-performance single-phase voltage regulator which has common arm between the AC/DC and DC/AC power converters and adopts appropriate switching strategy, resulting in the reduction of the number of switching devices. Moreover, by introducing the method to replace the method to replace the conventional AC condenser in filter circuit with the new low-cost type using two DC condenser, the whole voltage regulator system can be more compact, simpler and less expensive than conventional ones. The fully digital controller is designed using high speed DSP, and the proposed system is validated through the experimental results.

• Transactions on Electrical and Electronic Materials
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• 제18권5호
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• pp.257-260
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• 2017

In this paper, we present the design of a 4.5 V low dropout (LDO) voltage regulator implemented in the 130 nm CMOS process. The design uses a two-stage cascaded operational transconductance amplifier (OTA) as an error amplifier, with a body bias technique for reducing dropout voltages. PMOS is used as a pass transistor to ensure stable output voltages. The results show that the proposed LDO regulator has a dropout voltage of 32.06 mV when implemented in the130 nm CMOS process. The power dissipation is only 1.3593 mW and the proposed circuit operates under an input voltage of 5V with an active area of $703{\mu}m^2$, ensuring that the proposed circuit is suitable for low-power applications.

• 전기전자학회논문지
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• 제23권2호
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• pp.552-556
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• 2019

본 논문에서는 전류 제어 회로를 이용하여 load Transient response 특성을 향상시킨 capless LDO(low drop-out) 레귤레이터를 제안하였다. LDO 레귤레이터 내부의 오차증폭기와 패스 트랜지스터 사이에 전류 조절 회로를 두어 전압 라인에 들어오는 전류특성을 개선시켜 기존의 LDO 레귤레이터보다 향상된 transient 응답특성을 갖는다. 제안된 회로는 cadence의 virtuoso, spectre 시뮬레이터를 이용하여 0.18 um 공정에서 특성을 분석하였다. 실험 결과에 따르면, 제안된 회로 구성을 이용한 LDO의 load transient response는 기존 LDO과 비교하여 부하 전류가 rising time인 경우 1.954 us에서 1.378 us, falling time인 경우 19.48 us에서 13.33 us으로 약 29%, 28% 개선된 응답속도를 가진다.

• 대한전자공학회논문지SD
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• 제46권6호
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• pp.52-57
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• 2009

본 논문은 CMOS RFIC 단일 칩을 위한 Bandgap Voltage Reference와 이를 포함한 저 잡음 Low Dropout (LDO) Regulator 회로에 관한 것이다. 저 잡음을 위해 Bandgap Voltage Reference에 사용된 BJT 다이오드의 유효면적을 증가시켜야 함을 LDO의 잡음해석을 통해 나타내었다. 이를 위해 다이오드를 직렬 연결하여 실리콘의 실제면적은 최소화 하면서 다이오드의 유효면적을 증가시키는 방법을 적용하였고, 이를 통해 LDO의 출력잡음을 줄일 수 있음을 확인하였다. $0.18{\mu}m$ CMOS 공정으로 제작된 LDO는 입력전압이 2.2 V 에서 5 V 일때 1.8 V의 출력전압에서 최대 90 mA의 전류를 내보낼 수 있다. 측정 결과 Line regulation은 0.04%/V 이고 Load regulation은 0.45%를 얻었으며 출력 잡음 레벨은 100 Hz와 1 kHz offset에서 각각 479 nV/$^\surd{Hz}$와 186 nV/$^\surd{Hz}$의 우수한 성능을 얻었다.