• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2003년도 하계학술대회 논문집 C
• /
• pp.1821-1823
• /
• 2003

We propose a high voltage dc-dc converter for CW(continuous wave) $CO_2$ laser system using a current resonant half-bridge inverter and a Cockcroft-Walton circuit. This high voltage power supply includes a 2-stage voltage multiplier driven by a regulated half-bridge series resonant inverter. The inverter drives a step-up transformer and the transformer secondary is applied to the voltage multiplier. Thus, it has high efficiency because of the less switching losses by virtue of the current resonant half-bridge inverter, and also compact size, small parasitic capacitance in the transformer stage owing to the low number of a winding turn of the step up transformer secondary by combining with Cockroft-Walton circuit. We could be obtained the maximum laser output power of 44 W and the maximum system efficiency of over 16 %.

• 제어로봇시스템학회:학술대회논문집
• /
• 제어로봇시스템학회 2004년도 ICCAS
• /
• pp.1561-1564
• /
• 2004

A CMOS-based Electronically Tunable Capacitance Multipliers, which can be magnified the value of a grounded unit capacitance, is presented in this article. The multiplication factor is varied by the ratio of the bias currents. The proposed circuit is simple, small in size and suitable for implementing in standard CMOS process. PSPICE simulation results demonstrating the characteristics of the proposed circuit are included.

• 전기의세계
• /
• 제14권2호
• /
• pp.14-24
• /
• 1965

The characteristics of servo-multipliers and its accuracies are analyzed. From the analysis a low cost high accuracy four quadrant servo-multiplier with first derivative output feedback is built. The multiplier servomechanism has a second order system response with a damping ratio of 0.8 and computing bandwidth of 4 cycles per second, and its tracking accuracy at low speed of 0.5 volt per second is 0.9 per cent of maximum output voltage and static accuracy is better than 0.6 per cent. Method of testing this multiplier and the results are also described. The test on the characteristics of the multiplier shows that the results agree with theoretical values satisfactorily, and justifies the use of the servo-multiplier for slow type analog computers.

• 한국정보통신학회:학술대회논문집
• /
• 한국정보통신학회 2017년도 추계학술대회
• /
• pp.425-428
• /
• 2017

본 논문에서는 진동 에너지를 이용하여 에너지를 수확하는 전파 정류 하베스팅 회로를 설계하였다. 설계된 회로는 저전압에서도 전력효율이 우수하도록 Beta-Multiplier를 이용하여 Body-Bias technique을 Negative Voltage Converter에 적용하였으며, Comparator를 Bulk-Driven type으로 설계하였다. 제안된 회로는 $0.35{\mu}m$ CMOS 공정으로 설계하였으며, 설계된 회로의 칩 면적은 $931{\mu}m{\times}785{\mu}m$이다.

• 전기전자학회논문지
• /
• 제8권2호
• /
• pp.172-180
• /
• 2004

본 논문에서는 다치 논리회로를 구현하는 방식 중 전압 모드 방식에서 $neuron(\nu)MOS$ Down-literal circuit(DLC)의 다중 문턱전압 성질을 이용하여 유한체 $GF(3^m)$상에서 모든 항의 계수가 존재하는 기약 다항식에 대한 승산 알고리즘(AOTP)을 적용한 병렬 입-출력 모듈 구조의 승산기의 회로를 제안하였다. 3치 입력 신호가 인가되는 승산기는 뉴런모스 DLC를 이용하여 모듈화되고, 모듈에서 변환된 3치 입력 신호를 Pass 게이트를 통해서 선택하는 방식으로 승산 및 가산 게이트를 구현하였다. 설계된 승산기의 회로들은 +3V의 단일 공급 전원에서 $0.35{\mu}m$ N-well double-poly four-metal CMOS 공정의 모델 파라미터를 사용하여 모의실험이 수행되었다. 모의실험 결과를 통하여 승산기는 샘플링 레이트가 3MHz, 소비전력은 $4{\mu}W$, 출력은 ${\pm}0.1V$이내의 전압레벨을 유지하는 것을 알 수 있다.

• 제어로봇시스템학회:학술대회논문집
• /
• 제어로봇시스템학회 2002년도 ICCAS
• /
• pp.80.1-80
• /
• 2002

In this article, an alternative analog multiplier circuit, using the translinear second-generation current conveyors with the external resistors. The realization method makes use of the inherited translinear loop of the current conveyor offering the positive-supply current that provides in the quartersquare algebraic identity. The proposed circuit operates in voltage mode and it achieves a high accuracy. The PSPICE simulation results confirm that the performances of the proposed multiplier circuit, such as dynamic range and accuracy, are agreed with the theoretical results.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2003년도 학술회의 논문집 정보 및 제어부문 A
• /
• pp.79-82
• /
• 2003

This paper describes a new low-swing inverter for low power consumption. To reduce a power consumption, an output voltage swing is in the range from 0 to $V_{ref}-V_{TH}$, where $V_{ref}=V_{DD}-nV_{TH}$. This can be done by the inverter structure that allow a full swing or a swing on its input terminal without leakage current. Using this low-swing voltage technology, we propose a low-power $4\times4$ bit parallel multiplier. The proposed circuits are simulated with HSPICE under $0.35{\mu}m$ CMOS standard technology. Compare to the previous works, this circuit can reduce the power consumption rate of 11.2% and the power-delay product of 10.3%.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2008년도 하계종합학술대회
• /
• pp.537-538
• /
• 2008

A step-down DC-DC converter with On-chip Compensation for battery-operated portable electronic devices which are designed in 0.18um CMOS standard process. In an effort to improve low load efficiency, this paper proposes the PFM (Pulse Frequency modulation) voltage mode 1MHz switching frequency step-down DC-DC converter with on-chip compensation. Capacitor multiplier method can minimize error amplifier compensation block size by 20%. It allows the compensation block of DC-DC converter be easily integrated on a chip and occupy less layout area. But capacitor multiplier operation reduces DC-DC converter efficiency. As a result, this converter shows maximum efficiency over 87% for the output voltage of 1.8V (input voltage : 3.3V), maximum load current 500mA, and 0.14% output ripple voltage. The total core chip area is $mm^2$.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2003년도 학술회의 논문집 정보 및 제어부문 A
• /
• pp.267-270
• /
• 2003

This paper proposes high performance $8{\times}8$ multiplier using current-mode quaternary logic technique. The multiplier is functionally partitioned into the following major sections: partial product generator block(binary-quaternary logic conversion), current-mode quaternary logic full-adder block, quaternary-binary logic conversion block. The proposed multiplier has 4.5ns of propagation delay and 6.1mW of power consumption. Also, this multiplier can easily adapted to binary system by the encoder, the decoder. This circuit is simulated under 0.35um standard CMOS technology, 5uA unit current, and 3.3V supply voltage using Hspice.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2008년도 하계종합학술대회
• /
• pp.585-586
• /
• 2008

In this paper, a novel beta-multiplier reference current source circuit for the 800mV power-supply voltage is presented. In order to cope with the narrow input common-mode range of the OpAmp in the reference circuit, shunt resistive voltage divider branches were deployed. High gain OpAmp was designed to compensate intrinsic low output resistance of the MOS transistors. The proposed reference circuit was designed in a standard 0.18um CMOS process with nominal Vth of 420mV and -450mV for nMOS and pMOS transistor respectively. The total power consumption including OpAmp is less than 50uW.