• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.63-70
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• 2008

In this paper, a smart sensor system for the MEMS pressure sensor was developed. A compensation algorithm and programmable calibration circuits were presented to eliminate errors caused by temperature drift of piezoresistive pressure sensors in itself. This system consisted of signal conditioning, calibration, temperature detection, microprocessor, and communication parts and these were integrated into a SOC. A RS-232 interface was employed for monitoring and control of a smart sensor system. The area of fabricated IC is $4.38{\times}3.78\;mm^2$ and a $0.35{\mu}m$ high voltage CMOS process was used. Compensation error for temperature drift of 50 KPa pressure sensors was measured into ${\pm}0.48%$ in the range of $-40^{\circ}C{\sim}150^{\circ}C$. Total power consumption was 30.5 mW.

• The Journal of the Korea institute of electronic communication sciences
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• v.13 no.3
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• pp.539-546
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• 2018

Recently, as the solar power generation market is rapidly increasing, interest is focused on research for minimizing the output of the solar cell module. The role of the power optimizer is important when inconsistencies occur in photovoltaic power generation. In the conventional system, centralized inverter method and microinverter method are mainly used. In this paper, we analyze the problem of power generation efficiency loss due to the incompatibility of existing system configuration methods. We also proposed a module - type power compensation method that can improve the mismatch caused by shading. The proposed module - based power optimizer is implemented and compared with the existing operation method. From the simulation result, it was confirmed that the efficiency of the proposed operation method is improved compared to the existing method.

• Proceedings of the Materials Research Society of Korea Conference
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• 2011.10a
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• pp.30.1-30.1
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• 2011

Silicon is one of useful materials in various industry such as semiconductor, solar cell, and secondary battery. The metallic silicon produces generally melting process for ingot type or chemical vapor deposition (CVD) for thin film type. However, these methods have disadvantages of high cost, complicated process, and consumption of much energy. Electrodeposition has been known as a powerful synthesis method for obtaining metallic species by relatively simple operation with current and voltage control. Unfortunately, the electrodeposition of the silicon is impossible in aqueous electrolyte solution due to its low oxidation-reduction equilibrium potential. Ionic liquids are simply defined as ionic melts with a melting point below $100^{\circ}C$. Characteristics of the ionic liquids are high ionic conductivities, low vapour pressures, chemical stability, and wide electrochemical windows. The ionic liquids enable the electrochemically active elements, such as silicon, titanium, and aluminum, to be reduced to their metallic states without vigorous hydrogen gas evolution. In this study, the electrodeposion of silicon has been investigated in ionic liquid of 1-butyl-3-methylpyrolidinium bis (trifluoromethylsulfonyl) imide ([bmpy]$Tf_2N$) saturated with $SiCl_4$ at room temperature. Also, the effect of electrode materials on the electrodeposition and morphological characteristics of the silicon electrodeposited were analyzed The silicon electrodeposited on gold substrate was composed of the metallic Si with single crystalline size between 100~200nm. The silicon content by XPS analysis was detected in 31.3 wt% and the others were oxygen, gold, and carbon. The oxygen was detected much in edge area of th electrode due to $SiO_2$ from a partial oxidation of the metallic Si.

• The Journal of the Korea Contents Association
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• v.13 no.10
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• pp.54-61
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• 2013

This paper presents a simplified hardware based edge detection circuit which is based on an analog correlator combining with the neighbor pixels in CMOS image sensor. A pixel element of the edge detector consists of an active pixel sensor and an analog correlator circuit which connects two neighbor pixels. The edge detector shares a comparator on each column that the comparator decides an edge of the target pixel with an adjustable reference voltage. The circuit detects image edge from CIS directly that reduces area and power consumption 4 times and 20%, respectively, compared with the previous works. And also it has advantage to regulate sensitivity of the edge detection because the threshold value is able to control externally. The fabricated chip has 34% of fill factor and 0.9 ${\mu}W$ of power per a pixel under 0.18 ${\mu}m$ CMOS technology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.12
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• pp.31-38
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• 2010

This paper presents the design of a graphic memory for QVGA-scale LCD Driver IC (LDI). The graphic memory is designed based on the pseudo-SHAM for the purpose of small area, and the memory cell structure is designed using a bit line partitioning method to improve sensing characteristics and drivabilties in the line-read operation. Also, a collision protection circuit using C-gate is designed to control collisions between read/write operations and self-refresh/line-read operations effectively. The graphic memory circuit has been designed in transistor level using $0.18{\mu}m$ CMOS technology library and the operations of the graphic memory have been verified using Hspice. The results show that the bit-bitb line voltage difference, ${\Delta}V$ increases by 40%, the charge sharing time between bit and bitb voltages $T_{CHGSH}$ decreases by 30%, and the current during line-read decreases by 40%.

• Transactions of the Korean Society of Mechanical Engineers
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• v.7 no.3
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• pp.263-269
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• 1983

Underwater welding by a gravity arc welding process was investigated by using six types of coated electrodes and SM41A steel plates of 10 mm thickness as base metal and it was ascertained that this process may be put to practical use. Main results obtained are summarized as follows: 1. Angle of electrode affects no influence on bead appearance and the proper range of welding current and diameter of electrode for the high titanium oxide type is relatively wider than that for the ilmenite type. And the lime titania type, high titanium oxide type and ilmenite type of domestic coated arc welding electrodes of .phi.4 mm could attain the soundest underwater welded joints which contain no welding imperfection. 2. According to macro-structure, micro-structure and hardness distribution inspectionson underwater welded joint, the area between the HAZ and the surface of the weld in neighbourhood of the bond has the maximum hardness value. The structure of these parts is martensite and bainite. Other parts contain mocro-ferrite, micro-pearlite structure, which contain soundness of welded joint free from weld imperfection. 3. On consideration of both tensile strength of more than 100% joint efficiency and sufficient impact value, the welding condition which can get optimal welding strength is heat input of 1,400-1,500 J/mm, current of 200-215 ampere (voltage of 32-33 volts) in the case of lime titania type electrode. 4. Underwater welding strength (tensile strength, impact strength) depends on heat input (or current) quantitatively and they have the relationship of parabolic function. Each experimental equation has a high reliability and its percent of mean error is 4.14%. 5. It is suggested that the optimal design of weld strength by welding condition (current, heat input) could be utilized for a quality control of underwater welding.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.5
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• pp.899-905
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• 2017

This paper presents a reference-less dual loop clock and data recovery (CDR) circuit that supports a data rate of 2.496 Gb/s for the mobile industry processor interface (MIPI) M-PHY. An adaptive loop bandwidth scheme is used to implement the fast lock time maintaining a low time jitter. To this scheme, the proposed CDR consists of two loops for a frequency locked loop and a phase locked loop. The proposed 2.496 Gb/s reference-less dual loop CDR is designed using a 65 nm CMOS process with 1.2 V supply voltage. The simulated peak-to-peak jitter of output clock is 9.26 ps for the input data of 2.496 Gb/s pseudo-random binary sequence (PRBS) 15. The active area and power consumption of the implemented CDR are $470{\times}400{\mu}m^2$ and 6.49 mW, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.10
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• pp.2209-2216
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• 2011

In this paper, we design a 32-bit eFuse OTP memory for PMICs using MagnaChip's $0.18{\mu}m$ process. We solve a problem of an electrical shortage between an eFuse link and the VSS of a p-substrate in programming by placing an n-well under the eFuse link. Also, we propose a WL driver circuit which activates the RWL (read word-line) or WWL (write word-line) of a dual-port eFuse OTP memory cell selectively when a decoded WERP (WL enable for read or program) signal is inputted to the eFuse OTP memory directly. Furthermore, we reduce the layout area of the control circuit by removing a delay chain in the BL precharging circuit. We'can obtain an yield of 100% at a program voltage of 5.5V on 94 manufactured sample dies when measured with memory tester equipment.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.54 no.10
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• pp.438-442
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• 2005

Si nanocrystal (Si NC) memory device has several advantages such as better retention, lower operating voltage, reduced punch-through and consequently a smaller cell area, suppressed leakage current. However, the physical and electrical reasons for this behavior are not completely understood but could be related to interface states of Si NCs. In order to find out this effect, we characterized electrical properties of Si NCs embedded in a SiO$_{2}$ layer by scanning probe microscopy (SPM). The Si NCs were generated by the laser ablation method with compressed Si powder and followed by a sharpening oxidation. In this step Si NCs are capped with a thin oxide layer with the thickness of 1$\~$2 nm for isolation and the size control. The size of 51 NCs is in the range of 10$\~$50 m and the density around 10$^{11}$/cm$^{2}$ It also affects the interface states of Si NCs, resulting in the change of electrical properties. Using a conducting tip, the charge was injected directly into each Si NC, and the image contrast change and dC/dV curve shift due to the trapped charges were monitored. The results were compared with C-V characteristics of the conventional MOS capacitor structure.

• Journal of the Speleological Society of Korea
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• no.76
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• pp.37-42
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• 2006

The Dielectric Barrier Discharge (DBD) is a nonequilibrium gas discharge that is generated in the space between two electrodes, which are separated by an insulating dielectric layer. The dielectric layer can be put on either of the two electrodes or be inserted in the space between two electrodes. If an AC or pulse high voltage is applied to the electrodes that is operated at applied frequency from 50Hz to several MHz and applied voltages from a few to a few tens of kilovolts rms, the breakdown can occur in working gas, resulting in large numbers of micro-discharges across the gap, the gas discharge is the so called DBD. Compared with most other means for nonequilibrium discharges, the main advantage of the DBD is that active species for chemical reaction can be produced at low temperature and atmospheric pressure without the vacuum set up, it also presents many unique physical and chemical process including light, heat, sound and electricity. This has led to a number of important applications such as ozone synthesizing, UV lamp house, CO2 lasers, et al. In recent years, due to its potential applications in plasma chemistry, semiconductor etching, pollution control, nanometer material and large area flat plasma display panels, DBD has received intensive attention from many researchers and is becoming a hot topic in the field of non-thermal plasma.