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http://dx.doi.org/10.6109/jkiice.2017.21.5.899

A 2.496 Gb/s Reference-less Dual Loop Clock and Data Recovery Circuit for MIPI M-PHY  

Kim, Yeong-Woong (School of Electronic Engineering, Kumoh National Institute of Technology)
Jang, Young-Chan (School of Electronic Engineering, Kumoh National Institute of Technology)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.21, no.5, 2017 , pp. 899-905 More about this Journal
Abstract
This paper presents a reference-less dual loop clock and data recovery (CDR) circuit that supports a data rate of 2.496 Gb/s for the mobile industry processor interface (MIPI) M-PHY. An adaptive loop bandwidth scheme is used to implement the fast lock time maintaining a low time jitter. To this scheme, the proposed CDR consists of two loops for a frequency locked loop and a phase locked loop. The proposed 2.496 Gb/s reference-less dual loop CDR is designed using a 65 nm CMOS process with 1.2 V supply voltage. The simulated peak-to-peak jitter of output clock is 9.26 ps for the input data of 2.496 Gb/s pseudo-random binary sequence (PRBS) 15. The active area and power consumption of the implemented CDR are $470{\times}400{\mu}m^2$ and 6.49 mW, respectively.
Keywords
MIPI M-PHY; Clock and data recovery (CDR); Loop band-width control;
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