• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.169-174
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• 2014

As a versatile processing method for nanoscale memory integration, laser-induced epitaxial growth is proposed for the fabrication of vertical Si channel (VSC) transistor. The fabricated VSC transistor with 80 nm gate length and 130 nm pillar diameter exhibited field effect mobility of $300cm^2/Vs$, which guarantees "device quality". In addition, we have shown that this VSC transistor provides memory operations with a memory window of 700 mV, and moreover, the memory window further increases by employing charge trap dielectrics in our VSC transistor. Our proposed processing method and device structure would provide a promising route for the further scaling of state-of-the-art memory technology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.7 s.361
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• pp.16-23
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• 2007

For a fully depleted SOI type symmetric double gate MOSFET, a simple expression for the threshold voltage has been derived in a closed-form To solve analytically the 2D Poisson's equation in a silicon body, the two-dimensional potential distribution is assumed approximately as a polynomial of fourth-order of x, vertical coordinate perpendicular to the silicon channel. From the derived expression for the surface potential, the threshold voltage can be obtained as a simple closed-form. Simulation result shows that the threshold voltage is exponentially dependent on channel length for the range of channel length up to $0.01\;[{\mu}m]$.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.8
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• pp.78-88
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• 1992

To improve the characteristics of sub$\mu$m short channel MOSFET device, a new device having the convex structure is proposed. This device has 3-dimensionally expandable channel length according to the vertical etched silicon height. For the purpose of comparing the DC and AC characteristics, planar device is also fabricated. Comparing the channel length, the convex device with 0.4$\mu$m silicon height is larger about 0.56$\mu$m in NMOS and 0.78$\mu$m in PMOS than planar devices. DC characteristics, such as threshold voltage, operational current, substrate current and breakdown voltage are compared together with AC characteristics using the ring oscillator inverter delay. Also process and device simulation are performed and the differences between convex and pranaldevice are also compared.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.7
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• pp.1-6
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• 2002

For an optimum device design of nano-scale SOI devices, this paper describes the short channel effects of multi-gate structures SOI MOSFETs such as double gate, triple gate and quadruple gate, as well as a new proposed Pi gate using computer simulation. The simulation has been performed with different channel doping concentrations, channel widths, silicon film thickness, and vertical gate extension depths of Pi gate. From the simulation results, it is found that Pi gate devices have a large margin in determination of doping concentrations, channel widths and film thickness comparing to double and triple gate devices because Pi gate devices offer a better short channel effects.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.6
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• pp.758-765
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• 1986

The design, fabrication and performance of vertical double diffused power MOSFET (VDMOS) were described. On the antimony (Sb) doped (~7x10**17 cm**-3) silicon substrate (N+), epitaxial layer(N-) was grown. The thickness and the resistivity of this layer were 32\ulcorner and about 12\ulcorner-cm, respectively. The P- channel length which was controlled by sequential P-/N+ double diffuison method was about 1~2 \ulcorner, and was processed with the self alignment of 21 \ulcorner width poly silicon. To improve the breakdown voltage with constant on-resistance (Ron) about 1\ulcorner, three P+ guard rings were laid out around main pattern. With chip size of 4800\ulcorner x4840 \ulcorner, the VDMOS has shown breakdown voltage of 410~440V, on-resistance within 1.0~1.2\ulcornerand the current capablity of more than 5A.

• Transactions on Electrical and Electronic Materials
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• v.13 no.2
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• pp.73-77
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• 2012

Operation of liquid crystal displays (LCDs) can be improved by monolithic integration of the pixel transistors with light emitting diodes (LEDs) on a single substrate. Conventional LCDs make use of filters to control the backlighting which reduces the overall efficiency. These LCDs also utilize LEDs in series which impose failure and they require high voltage for operation with a power factor correction. The screen of small hand-held devices can operate from moderate brightness. Therefore, III-V nanowires that are grown along with transistors over Silicon substrates can be utilized. Control of nanowire LEDs with nanowire transistors will significantly lower the cost, increase the efficiency, improve the manufacturing yield and simplify the structure of the small displays that are used in portable devices. The steps to grow nanowires on Silicon substrates are described. The vertical n-type and p-type nanowire transistors with surrounding gate structures are characterized. While biased at 0.5 V, nanowire transistors with minimum radius or channel width have an OFF current which is less than 1pA, an ON current more than 1 ${\mu}A$, a total delay less than 10 ps and a transconductance gain of more than 10 ${\mu}A/V$. The low power and fast switching characteristics of the nanowire transistor make them an ideal choice for the realization of future displays of portable devices with long battery lifetime.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.49 no.1
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• pp.24-29
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• 2000

We propose a simple method to control the crystallization depth of amorphous silicon (a-Si) deposited by PECVD or LPCVD during the excimer laser annealing (ELA). Employing the new method, we have formed poly-Si/a-Si double film and fabricated a new poly-Si TFT with vertical a-Si offsets between the poly-Si channel and the source/drain of TFT without any additional photo-lithography process. The maximum leakage current of the new poly-Si TFT decreased about 80% due to the highly resistive vertical a-Si offsets which reduce the peak electric field in drain depletion region and suppress electron-hole pair generation. In ON state, current flows spreading down through broad a-Si cross-section in the vertical a-Si offsets and the current density in the drain depletion region where large electric field is applied is reduced. The stability of poly-Si TFT has been improved noticeably by suppressing trap state generation in drain region which is caused by high current density and large electric field. For example, ON current of the new TFT decreased only 7% at a stress condition where ON current of conventional TFT decreased 89%.

• Journal of Korean Society for Atmospheric Environment
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• v.27 no.3
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• pp.326-336
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• 2011

The Light Detection and Ranging (Lidar) observation provides a specific knowledge of the temporal and vertical distribution and the optical properties of the aerosols. Unlike typical Mie scattering Lidars, which can measure backscattering and depolarization, the Raman Lidar can measure the quartz signal at the ultra violet (360 nm) and the visible (546 nm) wavelengths. In this work, we developed a method for estimating mineral quartz concentration immersed in Asian dust using Raman scattering of quartz (silicon dioxide, silica). During the Asian dust period of March 15, 16, and 21 in 2010, Raman lidar measurements detected the presence of quartz, and successfully showed the vertical profile of the dust concentrations. The satellite observations such as the Moderate Resolution Imaging Spectroradiometer (MODIS) and the Cloud-Aerosol Lidar and Infrared Pathfinder Satellite Observations (CALIPSO) confirmed spatial distribution of Asian dust. This approach will be useful for characterizing the quartz dominated in the atmospheric aerosols and the investigations of mineral dust. It will be especially applicable for distinguishing the dust and non-dust aerosols in studies on the mixing state of Asian aerosols. Additionally, the presented method combined with satellite observations is enable qualitative and quantitative monitoring for Asian dust.

• Carbon letters
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• v.13 no.1
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• pp.17-22
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• 2012

Currently, graphene is a topic of very active research in fields from science to potential applications. For various radio-frequency (RF) circuit applications including low-noise amplifiers, the unique ambipolar nature of graphene field-effect transistors can be utilized for high-performance frequency multipliers, mixers and high-speed radiometers. Potential integration of graphene on Silicon substrates with complementary metal-oxide-semiconductor compatibility would also benefit future RF systems. The future success of the RF circuit applications depends on vertical and lateral scaling of graphene metal-oxide-semiconductor field-effect transistors to minimize parasitics and improve gate modulation efficiency in the channel. In this paper, we highlight recent progress in graphene materials, devices, and circuits for RF applications. For passive RF applications, we show its transparent electromagnetic shielding in Ku-band and transparent antenna, where its success depends on quality of materials. We also attempt to discuss future applications and challenges of graphene.