Journal of the Korean Institute of Telematics and Electronics (대한전자공학회논문지)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Design and Process of Vertical Double Diffused Power MOSFET Devices

이중확산 방법에 의한 수직구조형 전력용 MOSFET의 설계 및 공정

  • Yu, Hyun Kyu (Electronics and Telecommunications Research Institute) ;
  • Kwon, Sang Jik (Electronics and Telecommunications Research Institute) ;
  • Lee, Joong Whan (Electronics and Telecommunications Research Institute) ;
  • Kwon, Oh Joon (Electronics and Telecommunications Research Institute) ;
  • Kang, Young Il (Electronics and Telecommunications Research Institute)
  • 유현규 (한국전자통신연구소) ;
  • 권상직 (한국전자통신연구소) ;
  • 이중환 (한국전자통신연구소) ;
  • 권오준 (한국전자통신연구소) ;
  • 강영일 (한국전자통신연구소)
  • Published : 1986.06.01
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Abstract

The design, fabrication and performance of vertical double diffused power MOSFET (VDMOS) were described. On the antimony (Sb) doped (~7x10**17 cm**-3) silicon substrate (N+), epitaxial layer(N-) was grown. The thickness and the resistivity of this layer were 32\ulcorner and about 12\ulcorner-cm, respectively. The P- channel length which was controlled by sequential P-/N+ double diffuison method was about 1~2 \ulcorner, and was processed with the self alignment of 21 \ulcorner width poly silicon. To improve the breakdown voltage with constant on-resistance (Ron) about 1\ulcorner, three P+ guard rings were laid out around main pattern. With chip size of 4800\ulcorner x4840 \ulcorner, the VDMOS has shown breakdown voltage of 410~440V, on-resistance within 1.0~1.2\ulcornerand the current capablity of more than 5A.

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