• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.4
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• pp.103-109
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• 2007

This paper presents behavioral models using SIMULINK and Verilog-a for a PLL based fractional-N frequency synthesizer. By adopting a top-down approach along with the traditional bottom-up transistor level design in parallel, the design time is greatly shortened, and a co-verification method for both the digital and the analog part is considered. Under this consideration, the SIMULINK modeling reduces simulation time and easily estimates the PLL's performance on the top level. Verilog-a is able to verify the feasibility of each blocks at first hand because it is compatible with transister level circuits. Then, an efficient way of the design is presented by comparing the results of both models.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.3
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• pp.517-524
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• 2001

This paper describes a design of radix-2 SRT divider unit, which supports IEEE-754 floating-point standard, using redundant binary number system (RBNS). With the RBNS, the partial quotient decision logic can operate about 20-% faster, as well as can be implemented with a simple hardware when compared to the conventional methods based on two's complement arithmetic. By using a new redundant binary adder proposed in this paper, the mantissa divider is efficiently implemented, thus resulting in about 20% smaller area than other works. The divider unit supports double precision format, five exceptions and four rounding modes. It was verified with Verilog HDL and Verilog-XL.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.3
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• pp.211-215
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• 2009

As Programmable Logic Controllers (PLCs) are increasingly used to implement safety critical systems such as nuclear instrumentation & control system, formal verification for PLC based programs is becoming essential. This paper proposes a formal verification technique for PLC program implemented with function block diagram (FBD). In order to verify an FBD program, we translate an FBD program into a Verilog model and perform model checking using SMV model checker We developed a tool, FBD Verifier, which translates FBD programs into Verilog models automatically and supports efficient and intuitive visual analysis of a counterexample. With the proposed approach and the tool, we verified large FBD programs implementing reactor protection system of Korea Nuclear Instrumentation and Control System R&D Center (KNICS) successfully.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.06a
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• pp.682-684
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• 2007

This paper deals the application of sensor network system to fabricate wireless nodes. This node includes a CPLD(XC2C256), FPGA(XC3S1000) a RF module(Bim-433-F), a Hall Sensor and I also develop the CPLD(EPGA) controlling with Verilog-HDL using ISE. The network was consisst of a PC, a Sink node as a gateway, and three Sensor nodes. This sensor network can reaches 40 m with RF interface using by multi-path network.

• Journal of information and communication convergence engineering
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• v.19 no.4
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• pp.263-268
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• 2021

Although the compact capacitance model of point tunneling types of tunneling field-effect transistors (TFET) has been proposed, those of line tunneling types of TFETs have not been reported. In this study, a compact capacitance model of an L-shaped TFET (LTFET), a line tunneling type of TFET, is proposed using the previously developed surface potentials and current models of P- and L-type LTFETs. The Verilog-A LTFET model for simulation program with integrated circuit emphasis (SPICE) was also developed to verify the validation of the compact LTFET model including the capacitance model. The SPICE simulation results using the Verilog-A LTFET were compared to those obtained using a technology computer-aided-design (TCAD) device simulator. The current-voltage characteristics and capacitance-voltage characteristics of N and P-LTFETs were consistent for all operational bias. The voltage transfer characteristics and transient response of the inverter circuit comprising N and P-LTFETs in series were verified with the TCAD mixed-mode simulation results.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.3
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• pp.162-168
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• 2011

In this paper, we propose a new Verilog-A current-voltage model for multi-level-cell PCRAMs. This model can describe the PCRAM operation not only in full SET and RESET states but also in the partial resistance states. And, 3 PCRAM operating regions of SET-RESET, Negative Differential Resistance, and strong-ON are unified into one equation in this model thereby any discontinuity that may introduce a convergence problem cannot be found in the new PCRAM model. The percentage error between the measured data and this model is as small as 7.4% on average compared to 60.1% of the previous piecewise model. The parameter extraction which is embedded in the Verilog-A code can be done automatically.

• Journal of information and communication convergence engineering
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• v.11 no.2
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• pp.112-117
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• 2013

In order to reuse a register transfer level (RTL)-based IP block, it takes another architectural exploration in which the RTL will be put, and it also takes virtual platforms to develop the driver and applications software. Due to the increasing demands of new technology, the hardware and software complexity of organizing embedded systems is growing rapidly. Accordingly, the traditional design methodology cannot stand up forever to designing complex devices. In this paper, I introduce an electronic system level (ESL)-based approach to designing complex hardware with a derivative of SystemVerilog. I adopted the concept of reuse with higher levels of abstraction of the ESL language than traditional HDLs to design multiplication server farms. Using the concept of ESL, I successfully implemented server farms as well as a test bench in one simulation environment. It would have cost a number of Verilog/C simulations if I had followed the traditional way, which would have required much more time and effort.

• Proceedings of the Korean Information Science Society Conference
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• 2005.11a
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• pp.610-612
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• 2005

EPON은 점대다점 구조를 가지기 때문에 ONU에서 OLT로 데이터를 전송하는 상향 트래픽 전송에서 전송매체를 공유함에 따라 충돌이 발생하게 된다. 그러므로 모든 사용자가 공정한 매체 접근 권한을 가지고 경쟁 없이 전송을 하기 위한 매체접근 제어 기술이 필수적이다. RC-DBA 알고리즘은 버스트 트래픽 지원과 ONU들 사이의 공정성 지원 등의 장점을 가진 매체접근 제어 알고리즘이다. 본 논문에서는 RC-DBA 알고리즘을 적용한 OLT와 간단한 ONU를 하드웨어 기술 언어인 Verilog HDL을 사용하여 작성하고 시뮬레이션을 해봄으로써 그 기능을 검증하였다.

• ETRI Journal
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• v.33 no.1
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• pp.50-59
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• 2011

In the current very deep submicron technology era, fault tolerant mechanisms perform an essential function to cope with the effects of soft errors. To evaluate the effectiveness of the fault tolerant mechanism, reliability engineers use simulated fault injections using either saboteur modules or mutants in the simulation model. However, the two methods suffer from both inefficiency in the simulation mechanism and difficulties with the experimental setups. To overcome these inefficiencies, we propose the Verilog-based simulated fault injection (VFI) technique. VFI has the following advantages. First, modification of the design model is unnecessary. Second, the fault injection simulation procedure is simple and efficient. Third, various types of fault injection experiments can be performed. To evaluate the effectiveness of the proposed methodology, we developed a VFI environment using the ICARUS Verilog Simulator. From the experimental results, we were able to qualitatively evaluate the reliability of the target simulation models and to assess the effectiveness of the employed fault-tolerance mechanisms.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.78-85
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• 2008

This paper presents a high-level design methodology applied on an SoC using SystemC. The topic will emphasize on high-level design approach for intensive architecture exploration and verifying cycle accurate SystemC models comparative to real Verilog RTL models. Unlike many high-level designs, we started the poject with working Verilog RTL models in hands, which we later compared our SystemC models to real Verilog RTL models. Moreover, we were able to use the on-chip test board performance simulation data to verify our SystemC-based platform. This paper illustrates that in high-level design, we could have the same accuracy as RTL models but achieve over one hundred times faster simulation speed than that of RTL's. The main topic of the paper will be on architecture exploration in search of performance degradation in source.