1 |
Kanishka Lahiri, Anand Raghunathan, and Sujit Dey, "Design Space Exploration for Optimizing On-Chip Communication Architectures", IEEE Trans. Computer-Aided Design, vol. 23, pp.952-961, June. 2004
DOI
ScienceOn
|
2 |
http://www.arm.com
|
3 |
http://www.sun.com/desktop/FinalSB2000ds.pdf
|
4 |
Preeti Ranjan Panda: "SystemC. A modeling platform supporting multiple design abstractions", Synopsys Inc, http://www.synopsys.com
|
5 |
http://www.uclinux.org
|
6 |
CoCentric System Studio Data Sheet, Synopsys http://www.synopsys.com
|
7 |
http://www.cadence.com/verisity/
|
8 |
K. Lahiri, A. Raghunathan, G. Lakshminarayana, and S. Dey, "Communication architecture tuners: A methodology for the design of high performance communication architectures for system-on-chips," in Proc. Design Automation Conf., June 2000, pp. 513-518
|