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A SIMULINK Modeling for a Fractional-N Frequency Synthesizer  

Kim, In-Jeong (Department of Electrical Engineering, Kookmin University)
Seo, Woo-Hyong (Department of Electrical Engineering, Kookmin University)
Ahn, Jin-Oh (Department of Electrical Engineering, Kookmin University)
Kim, Dae-Jeong (Department of Electrical Engineering, Kookmin University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.44, no.4, 2007 , pp. 103-109 More about this Journal
Abstract
This paper presents behavioral models using SIMULINK and Verilog-a for a PLL based fractional-N frequency synthesizer. By adopting a top-down approach along with the traditional bottom-up transistor level design in parallel, the design time is greatly shortened, and a co-verification method for both the digital and the analog part is considered. Under this consideration, the SIMULINK modeling reduces simulation time and easily estimates the PLL's performance on the top level. Verilog-a is able to verify the feasibility of each blocks at first hand because it is compatible with transister level circuits. Then, an efficient way of the design is presented by comparing the results of both models.
Keywords
fractional-N frequency synthesizer; behavioral modeling; Verilog-a; simulink; top-down design;
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