Browse > Article

A Formal Verification Technique for PLC Programs Implemented with Function Block Diagrams  

Jee, Eun-Kyoung (KAIST 전자전산학과)
Jeon, Seung-Jae (삼성전자 영상디스플레이사업부)
Cha, Sung-Deok (고려대학교 컴퓨터통신공학부)
Publication Information
Journal of KIISE:Computing Practices and Letters / v.15, no.3, 2009 , pp. 211-215 More about this Journal
Abstract
As Programmable Logic Controllers (PLCs) are increasingly used to implement safety critical systems such as nuclear instrumentation & control system, formal verification for PLC based programs is becoming essential. This paper proposes a formal verification technique for PLC program implemented with function block diagram (FBD). In order to verify an FBD program, we translate an FBD program into a Verilog model and perform model checking using SMV model checker We developed a tool, FBD Verifier, which translates FBD programs into Verilog models automatically and supports efficient and intuitive visual analysis of a counterexample. With the proposed approach and the tool, we verified large FBD programs implementing reactor protection system of Korea Nuclear Instrumentation and Control System R&D Center (KNICS) successfully.
Keywords
Programmable Logic Controller; Function Block Diagram; Formal Verification; Model Checking; Counterexample Analysis;
Citations & Related Records
연도 인용수 순위
  • Reference
1 Standard Hardware Description Language Based on the Verilog Hardware Description Language (Std 1364-2001), IEEE, 2003
2 Jain, H., Sharygina, N., Kroening, D. and Clarke, E., "Word Level Predicate Abstraction and Re-finement for Verifying RTL Verilog," In Proc. 42nd Design Automation Conference (DAC), Anaheim, USA, 2005
3 Bani Younis. M, and Frey, G., “Formalization of Existing PLC Programs: A Survey,” Proceedings of CESA 2003, Lille, France, July 9-11, 2003
4 International Standard for Programmable Controllers: Programming Languages (Part 3), IEC, 1993
5 원전계측제어시스템 개발사업단 (KNICS: Korea Nuclear Instrumentation and Control System Research and Development Center), http://www.knics. re.kr
6 Baresi, L., Mauri, M., Monti, A. and Pezze, M., “PLCTOOLS: Design, Formal Validation, and Code Generation for Programmable Controllers,” FormaI methods in PLC programming Special Session at IEEE Conference on Systems, Man and Cybernetics (SMC'2000), Nashville, USA, Oct. 8-11, 2000   DOI
7 KNICS-RPS-SDS231 (Rev.02), 원자로보호계통 소프트웨어 설계 명세서, 두산중공업(주), 2007
8 Mader, A., “A Classification of PLC Models and Applications,” Proc. WODES 2000: 5th Workshop on Discrete Event Systems, Gent, Belgium, Aug. 21-23, 2000
9 유준범, "NuSCR 정형명세로부터 Function Block Diagrams의 생성", 박사학위논문, KAIST, 2005
10 sm2vcd, $http://www.cs.cmu.edu/^{~}modelcheck/sm2vcd.html$
11 CBMC, Bounded Model Checking for ANSI-C, $http://www.cs.cmu .edu/^{~}modelcheck/cbmc$