• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.4
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• pp.101-112
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• 2004

In this paper, we developed a numerical analysis model by using ADI-FDTD method to analyze three-dimensional interconnect structure. We discretized maxwell's curl equation by using ADI-FDTD. Using ADI-FDTD method, a sampler circuit designed from 3.3 V CMOS technology is simplified to 3-metal line structure. Using this simplified structure, the time delay and signal distortion of complex interconnects are investigated. As results of simulation, 5∼10 ps of delay time and 0.1∼0.2 V of signal distortion are measured. As demonstrated in this paper, the full-wave analysis using ADI-FDTD exhibits a promise for accurate modeling of electromagnetic phenomena in high-speed VLSI interconnect.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.53-59
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• 2004

This paper proposes an efficient method for computing the 3-dimensional capacitance of complex structures. The proposed method is based on applying numerical 2-dimensional capacitance extraction formula for 3-dimensional interconnect models. This method improves the extraction efficiency 952 times while compromising the accuracy within 1.8 percentage of maximal relative error, compared with the results of Fastcap program for various 3-D models. The proposed method can be used efficiently to extract electrical parameters of on/off-chip interconnects in VLSI systems.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.9
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• pp.78-85
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• 2000

A new analytical VLSI interconnect delay model is presented and its accuracy is experimentally verified. In the model, the transmission line parameter variations due to skin effect, proximity effect, and silicon substrate effect are taken into account. That is, the circuit model of the interconnect line that includes these effects is newly developed and analyzed. For the model verification, test patterns combined the coplanar structure with microstrip were designed by using 0.35${\mu}m$ CMOS process technology. It is shown that the accuracy of the model is less than about 10% error.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.3
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• pp.25-33
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• 2011

As chip operating frequency increases, there is growing concern about on-chip interconnect inductance. This paper presents a two-step inductance screening tool to select interconnects with significant inductance effects in a VLSI design. Test chips designed in different CMOS technology nodes are examined. The inductance screening results show that 0.1% of the nets in a design have inductance problems with chips running at its operating frequency, supporting the necessity of a screening process instead of adding inductance model to all the nets in the design. The increase in resistance due to geometry scaling will strongly affect the significance of inductance on delay as technology and frequency scale. Since higher frequency worsens inductance problem and geometry scaling alleviates it, inductance screening tool can provide useful guidelines to circuit designers.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.650-653
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• 2002

The increaseing speeds are accompanied by decreases in pulse rise and fall time in VLSI circuits. These accenturate the high frequency spectral contents of the signals and cause the frequency dependent loss of the conductors which interconnect the various sub-circuits composing of VLSI circuit. The lossy effect is approximated by the square root of frequency dependence of the per unit length resistance. In the practical applications, several problems may arise along with this approximation, so we extend our investigation of the lossy effect by numerical Laplace inversion method.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.4
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• pp.260-266
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• 2007

Analytical compact form models for the signal transients and crosstalk noise of inductive-effect-prominent multi-coupled RLC lines are developed. Capacitive and inductive coupling effects are investigated and formulated in terms of the equivalent transmission line model and transmission line parameters for fundamental modes. The signal transients and crosstalk noise expressions of two coupled lines are derived by using a waveform approximation technique. It is shown that the models have excellent agreement with SPICE simulation.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.439-442
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• 2004

Timing delays due to VLSI circuit interconnects strongly depend on neighbor line switching patterns as well as input transition time. Considering both the input transition and input switching pattern, a new analytical timing delay model is developed by using the decoupling technique of transfer multi-coupled lines into an effective single line. The analytical timing delay model can determine the timing delay of multi-coupled lines accurately as well as rapidly. It is verified by using DSM-Technology ($0.1{\mu}m$ /low-k copper-based process) that the model has excellent agreement with the results of SPICE simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.3
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• pp.73-84
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• 2002

Fast and accurate new capacitance determination methodology for non-uniform complicated multi-layer VLSI interconnects is presented. Since a capacitance determination of intricate multi-layer interconnects using 3-dimensional field-solver is not practical, quasi-3-dimensional methodology is presented. Interconnects with discontinuity (i.e., bend structure and different spacing between lines, etc.) are partitioned. Then, each partial capacitance of divided parts is extracted by using 2-dimensional extraction methodology. For a multi-layer interconnects with shielding layer, the system can be simplified by investigating a distribution of charge in it. Thereby, quasi-3-dimensional capacitance for multi-layer interconnects can be determined by combining solid-ground based 2-dimensional capacitance and shielding effect which is independently determined with layout dimensions. This methodology for complicated multi-layer interconnects is more accurate and cost-efficient than conventional 3-dimensional methodology It is shown that the quasi-3-dimensional capacitance methodology has excellent agreement with 3-dimensional field- solver-based results within 5% error.

• Journal of Korea Spatial Information System Society
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• v.7 no.2 s.14
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• pp.57-66
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• 2005

The Interconnecting Highways problem is an abstract of many practical Layout Design problems in the areas of VLSI design, the optical and wired network design, and the planning for the road constructions. For the road constructions, the shortest-length road layouts that interconnect existing positions will provide many more economic benefits than others. That is, finding new road layouts to interconnect existing roads and cities over a wide area is an important issue. This paper addresses an approximation scheme that finds near optimal road layouts for the Interconnecting Highways problem which is NP-hard. As long as computational resources are provided, the near optimality can be acquired asymptotically. This implies that the result of the scheme can be regarded as the optimal solution for the problem in practice. While other approximation schemes can be made for the problem, this proposed scheme provides a big merit that the algorithm designed by this scheme fits well to given problem instances.

• Journal of Electrical Engineering and information Science
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• v.2 no.5
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• pp.17-26
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• 1997

Interconnect characterization on a wafer level was performed. Test patterns for single, two-coupled, and triple-coupled lines ere designed by using 0.5$\mu\textrm{m}$ CMOS process. Then interconnect capacitances and resistances were experimentally extracted by using tow port network measurements, Particularly to eliminate parasitic effects, the Y-parameter de-embedding was performed with specially designed de-embedding patterns. Also, for the purpose of comparisons, capacitance matrices were calculated by using the existing CAD model and field-solver-based commercial simulator, METAL and MEDICI. This work experimentally verifies that existing CAD models or parameter extraction may have large deviation from real values. The signal transient simulation with the experimental data and other methodologies such as field-solver-based simulation and existing model was performed. as expected, the significantly affect on the signal delay and crosstalk. The signal delay due to interconnects dominates the sub-micron-based a gate delay (e.g., inverter). Particularly, coupling capacitance deviation is so large (about more than 45% in the worst case) that signal integrity cannot e guaranteed with the existing methodologies. The characterization methodologies of this paper can be very usefully employed for the signal integrity verification or he electrical design rule establishments of IC interconnects in the industry.