Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)

The Institute of Electronics and Information Engineers (대한전자공학회)
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An Analytical Switching-Dependent Timing Model for Multi-Coupled VLSI Interconnect lines

디커플링 방법을 이용한 RC-Coupled 배선의 해석적 지연시간 예측 모델

  • Kim, Hyun-Sik (Hanyang University, Dept. of Electrical and Computer Engineering) ;
  • Eo, Yung-Seon (Hanyang University, Dept. of Electrical and Computer Engineering) ;
  • Shim, Jong-In (Hanyang University, Dept. of Electrical and Computer Engineering)
  • 김현식 (한양대학교 전자전기제어 계측공학과) ;
  • 어영선 (한양대학교 전자전기제어 계측공학과) ;
  • 심종인 (한양대학교 전자전기제어 계측공학과)
  • Published : 2004.06.01
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Abstract

Timing delays due to VLSI circuit interconnects strongly depend on neighbor line switching patterns as well as input transition time. Considering both the input transition and input switching pattern, a new analytical timing delay model is developed by using the decoupling technique of transfer multi-coupled lines into an effective single line. The analytical timing delay model can determine the timing delay of multi-coupled lines accurately as well as rapidly. It is verified by using DSM-Technology ($0.1{\mu}m$ /low-k copper-based process) that the model has excellent agreement with the results of SPICE simulation.

Keywords