• Journal of the Institute of Electronics Engineers of Korea SC
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• v.38 no.1
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• pp.27-34
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• 2001

The multiplication algorithm using the primitive irreducible trinomial $x^m+x+1$ over $GF(2^m)$ was proposed by Mastrovito. The multiplier proposed in this paper consisted of the multiplicative operation unit, the primitive irreducible operation unit and mod operation unit. Among three units mentioned above, the Primitive irreducible operation was modified to primitive irreducible trinomial $x^m+x+1$ that satisfies the range of 1$x^m,{\cdots},x^{2m-2}\;to\;x^{m-1},{\cdots},x^0$ is reduced. In this paper, the primitive irreducible polynomial was reduced to the primitive irreducible trinomial proposed. As a result of this reduction, the primitive irreducible trinomial reduced the size of circuit. In addition, the proposed design of multiplier was suitable for VLSI implementation because the circuit became regular and modular in structure, and required simple control signal.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.12
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• pp.60-69
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• 2000

This paper describes a single-chip full-custom implementation of pipelined adaptive decision-feedback equalizer(PADFE) using a 0.25-${\mu}m$ CMOS technology for wide-band wireless digital communication systems. To enhance the throughput rate of ADFE, two pipeline stages are inserted into the critical path of the ADFE by using delayed least-mean-square(DLMS) algorithm. Redundant binary (RB) arithmetic is applied to all the data processing of the PADFE including filter taps and coefficient update blocks. When compared with conventional methods based on two's complement arithmetic, the proposed approach reduces arithmetic complexity, as well as results in a very simple complex-valued filter structure, thus suitable for VLSI implementation. The design parameters including pipeline stage, filter tap, coefficient and internal bit-width, and equalization performance such as bit error rate (BER) and convergence speed are analyzed by algorithm-level simulation using COSSAP. The single-chip PADFE contains about 205,000 transistors on an area of about $1.96\times1.35-mm^2$. Simulation results show that it can safely operate with 200-MHz clock frequency at 2.5-V supply, and its estimated power dissipation is about 890-mW. Test results show that the fabricated chip works functionally well.

• Transactions on Electrical and Electronic Materials
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• v.17 no.2
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• pp.92-97
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• 2016

This paper presents design and simulation of wide band RF microswitch that uses electrostatic actuation for its operation. RF MEMS devices exhibit superior high frequency performance in comparison to conventional devices. Similar techniques that are used in Very Large Scale Integration (VLSI) can be employed to design and fabricate MEMS devices and traditional batch-processing methods can be used for its manufacturing. The proposed switch presents a novel design approach to handle reliability concerns in MEMS switches like dielectric charging effect, micro welding and stiction. The shape has been optimized at actuation voltage of 14-16 V. The switch has an improved restoring force of 20.8 μN. The design of the proposed switch is very elemental and primarily composed of electrostatic actuator, a bridge membrane and coplanar waveguide which are suspended over the substrate. The simple design of the switch makes it easy for fabrication. Typical insertion and isolation of the switch at 1 GHz is -0.03 dB and -71 dB and at 85 GHz it is -0.24 dB and -29.8 dB respectively. The isolation remains more than - 20 db even after 120 GHz. To our knowledge this is the first demonstration of a metal contact switch that shows such a high and sustained isolation and performance at W-band frequencies with an excellent figure-of merit (fc=1/2.pi.Ron.Cu =1,900 GHz). This figure of merit is significantly greater than electronic switching devices. The switch would find extensive application in wideband operations and areas where reliability is a major concern.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.3
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• pp.628-636
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• 2010

In this paper, we present a new type high speed parallel multiplier for performing the multiplication of two polynomials using standard basis in the finite fields GF($2^m$). Prior to construct the multiplier circuits, we design the basic cell of vector code generator(VCG) to perform the parallel multiplication of a multiplicand polynomial with a irreducible polynomial and design the partial product result cell(PPC) to generate the result of bit-parallel multiplication with one coefficient of a multiplicative polynomial with VCG circuits. The presented multiplier performs high speed parallel multiplication to connect PPC with VCG. The basic cell of VCG and PPC consists of one AND gate and one XOR gate respectively. Extending this process, we show the design of the generalized circuits for degree m and a simple example of constructing the multiplier circuit over finite fields GF($2^4$). Also, the presented multiplier is simulated by PSpice. The multiplier presented in this paper uses the VCGs and PPCS repeatedly, and is easy to extend the multiplication of two polynomials in the finite fields with very large degree m, and is suitable to VLSL.

• Journal of IKEEE
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• v.12 no.1
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• pp.1-7
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• 2008

With the recent development of portable system such as mobile communication and multimedia. Full adders are important components in applications such as digital signal processors and microprocessors. Thus It is important to improve the power dissipation and operating speed for designing a full adder. We propose a new adder with modified version of conventional Ratioed logic and Pass Transistor logic. The proposed adder has the advantages over the conventional CMOS, TGA, 14T logic. The delay time is improved by 13% comparing to the average value and PDP(Power Delay Product) is improved by 9% comparing to the average value. Layouts have been carried out using a 0.18um CMOS design rule for evaluation purposes. The physical design has been evaluated using HSPICE.

• The KIPS Transactions:PartA
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• v.15A no.1
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• pp.61-68
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• 2008

In this paper, we propose the VLSI design of Multi-Format Video Decoder (MFD) to support video codec standards such as MPEG-2, MPEG-4, H.264 and VC-1. The target of the proposed MFD is the Full HD (High Definition) video processing needed for the high-end D-TV SoC (System-on-Chip). The size of the design is reduced by sharing the common large-size resources such as the RISC processor and the on-chip memory among the different codecs. In addition, a detachable architecture is introduced in order to easily add or remove the codecs. The detachable architecture preserves the stability of the previously designed and verified codecs. The size of the design is about 2.4 M gates and the operating clock frequency is 225MHz in the Samsung 65nm process. The proposed MFD supports more than Full-HD (1080p@30fps) video decoding, and the largest number of video codec standards known so far.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.3
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• pp.555-562
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• 2008

In this paper we proposed a practical low-power design technique using clock-gating in RTL. An efficient low-power methodology is that a high-level designer analyzes a generic system and designs a controller for clock-gating. Also the desirable flow is to derive clock-gating in normal synthesis process by synthesis tool than to insert directly gate to clock line. If low-power is considered in coding process, clock is gated in coding process. If not considered, after analyzing entire operation. clock is Bated in periods of holding data. After analyzing operation for clock-gating, a controller was designed for it, and then a low-power circuit was generated by synthesis tool. From result, we identified that the consumed power of register decreased from 922mW to 543mW, that is the decrease rate is 42%. In case of synthesizing the test circuit using synthesizer of Power Theater, it decreased from 322mW to 208mW (36.5% decrease).

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.740-743
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• 2008

본 연구에서는 MicroTec을 이용하여 MOSFET Process 설계를 구현하였다. MOS(Metal Oxide Semiconductor)는 실리콘 기판 등의 반도체 표면에 산화막을 입히고 그 위에 금속을 부착시킨 구조이다. MOSFET의 응용은 VLSI 회로에만 제한되지 않고 전력-전자 회로에서 중요한 역할을 하며 점점 더 적용범위를 증가시켜 마이크로파 응용에 이르기까지 광범위하게 사용하고 있다. Process를 구연하는 방법은 Grid의 크기를 지정하고, 기판의 원소는 B로 지정하고 $1{\times}10^{15}/cm^3$ 만큼 도핑한다. 기판에 구멍을 내어 B와 As의 도핑농도와 에너지값을 설정한다. 마지막으로 어넬링 파라미터 값을 설정한다. 본 연구에서는 원소의 도핑값과 에너지값의 변화에 따른 MOSFET Process의 변화를 알 수 있었다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.11
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• pp.2291-2302
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• 1994

This paper shows the implementation and design of special processor for linearly shift knapsack public key cryptography system. We highten the density of existing knapsack vector and shift the vectors linearly in order to implement the structure of linearly shift knapsack system which has the stronger cryptosystem. As it needs the parallel processing at each path according to the characteristics of this system. we propose the pipelined parallel structure and implement this system into VLSL. Also we evaluate this system and compare with other systems. The processing speed of this system is 550kb/s when dimension is 100. It is possible to use this system at the place of requiring high speed security to enlarge the structure of it.

• Journal of Computing Science and Engineering
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• v.6 no.2
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• pp.79-88
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• 2012

Power continues to be a driving force in central processing units (CPU) design. Most of the advanced breakthroughs in power have been in a realm that is applicable to workstation CPUs. Advanced power management systems will manage temperature, dynamic voltage scaling and dynamic frequency scaling in a CPU. The use of power management systems for microcontrollers and embedded CPUs has been modest, and mostly focuses on very large scale integration (VLSI) level optimizations compared to system level optimizations. In this paper, a dynamic frequency controlling (DFC) technique is introduced, to lay the foundation of a system level power management system for commercial microcontrollers. The DFC technique allows a commercial microcontroller to have minor modifications on both the hardware and software side, to allow the clock frequency to change to save power; results in this study show a 10% savings. By adding an additional layer of software abstraction at the interrupt level, the microcontroller can operate without having knowledge of the current clock frequency, and this can be accomplished without having to use an embedded operating system.