• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2004.11b
• /
• pp.7-12
• /
• 2004

New modular Lateral Information Propagation Networks(LIPN) has been designed. The LIPN has shown to be useful for interpolation of information[3]. The problem is the fact that only the small number of nodes can be implemented in a IC chip with the circuit VLSI technology. The proposed modular architecture is for enlarging the neural network through inter module connections. For such inter module connections, the host(computer or logic) mediates the exchange of information among modules. Also border nodes in each module have capacitors for temporarily retaining the information from outer modules. Simulation of interpolation with the designed LIPN has been done through various experiments.

• Proceedings of the IEEK Conference
• /
• 2000.07a
• /
• pp.347-350
• /
• 2000

We present the design of ternary flip-flop which is based on ternary logic so as to process ternary data. These flip-flops are fabricated with ternary voltage mode NOR, NAND, INVERTER gates. These logic gate circuits are designed using CMOS and obtained the characteristics of a lower voltage, a lower power consumption as compared to other gates. These circuits have been simulated with the electrical parameters of a standard 0.25 micron CMOS technology and 2.5 volts supply voltage. The Architecture of proposed ternary flip-flop is highly modular and well suited for VLSI implementation, only using ternary gates.

• Proceedings of the KIEE Conference
• /
• 1998.07g
• /
• pp.2206-2208
• /
• 1998

The modular Lateral Information Propagation Networks(LIPN) has been designed. The LIPN has shown to be useful for interpolation of information[3]. The problem is the fact that only the small number of nodes can be implemented in a IC chip with the circuit VLSI technology. The proposed modular architecture is for enlarging the neural network through inter module connections. For such inter module connections, the host(computer or logic) mediates the exchange of information among modules. Also border nodes in each module have capacitors for temporarily retaining the information from outer modules. The LIPN with $4{\times}4$ modules has been designed and simulation of interpolation with the designed LIPN has been done.

• Proceedings of the IEEK Conference
• /
• 2000.07b
• /
• pp.811-814
• /
• 2000

It this paper a VLSI architecture of the Shape-Adaptive Discrete Cosine Transform (SA-DCT) is described, which can be employed dedicatedly for MPEG-4 video codec. Adopting a fast DCT algorithm, the number of multipliers can be reduced by half in comparison with a conventional algorithm. This SA-DCT core with a small additional amount of hardware can perform the SA-Inverse DCT (SA-IDCT) by sharing multipliers and a transportation memory. The proposed SA-DCT core is integrated with 40,000 gates by using 0.35$mu$m triple-metal CMOS technology, which operates at 20 Mhz, and hence enables the realtime codec of CIF ($352{\times}288$ pixels) pictures.

• The Transactions of the Korean Institute of Electrical Engineers
• /
• v.45 no.2
• /
• pp.319-324
• /
• 1996

Using random pulse stream, a number can be transformed to the pulse stream with the probability value. So the digital value are computed by simple digital gates. Thus it will be possible to build a small and strong noise immunity processing element. We propose a faster convergence algorithm using a new methods for better performance of Random Number Generator(RNG) an the nonlinear transfer function(Sigmoid function)in this paper. And a feedback circuit were fitted for pulse stream in this paper. We proposed method is simulated with C program language and conformed by circuit implementation. Finally a system for hand written number recognition is constructed by FPGA and its performance verified.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.12
• /
• pp.45-52
• /
• 2005

A systolic array formed by interconnecting a set of identical data-processing cells in a uniform manner is a combination of an algorithm and a circuit that implements it, and is closely related conceptually to arithmetic pipeline. High-performance computation on a large array of cells has been an important feature of systolic array. To achieve even higher degree of concurrency, it is desirable to make cells of systolic array themselves systolic array as well. The structure of systolic array with its cells consisting of another systolic array is to be called super-systolic array. This paper proposes a scalable bit-level super-systolic amy which can be adopted in the VLSI design including regular interconnection and functional primitives that are typical for a systolic architecture. This architecture is focused on highly regular computational structures that avoids the need for a large number of global interconnection required in general VLSI implementation. A bit-level super-systolic FIR filter is selected as an example of bit-level super-systolic array. The derived bit-level super-systolic FIR filter has been modeled and simulated in RT level using VHDL, then synthesized using Synopsys Design Compiler based on Hynix $0.35{\mu}m$ cell library. Compared conventional word-level systolic array, the newly proposed bit-level super-systolic arrays are efficient when it comes to area and throughput.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.40 no.11
• /
• pp.51-62
• /
• 2003

This paper presents a novel survivor memeory management and decoding techniques with sequential backward state transition control in the trace back Viterbi decoder. The Viterbi algorithm is an maximum likelihood decoding scheme to estimate the likelihood of encoder state for channel error detection and correction. This scheme is applied to a broad range of digital communication such as intersymbol interference removing and channel equalization. In order to achieve the area-efficiency VLSI chip design with high throughput in the Viterbi decoder in which recursive operation is implied, more research is required to obtain a simple systematic parallel ACS architecture and surviver memory management. As a method of solution to the problem, this paper addresses a progressive decoding algorithm with sequential backward state transition control in the trace back Viterbi decoder. Compared to the conventional trace back decoding techniques, the required total memory can be greatly reduced in the proposed method. Furthermore, the proposed method can be implemented with a simple pipelined structure with systolic array type architecture. The implementation of the peripheral logic circuit for the control of memory access is not required, and memory access bandwidth can be reduced Therefore, the proposed method has characteristics of high area-efficiency and low power consumption with high throughput. Finally, the examples of decoding results for the received data with channel noise and application result are provided to evaluate the efficiency of the proposed method.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.11
• /
• pp.123-130
• /
• 2004

This paper describes a multiplier architecture optimized for 32 bit RISC processor with 3-stage pipeline. The multiplier of ARM7, the target processor, is variably carried out on the execution stage of pipeline within 7 cycles. The included multiplier employs a modified Booth's algerian to produce 64 bit multiplication and addition product and it has 6 separate instructions. We analyzed several multiplication algorithm such as radix4-32${\times}$8, radix4-32${\times}$16 and radix8-32${\times}$32 to decide which multiplication architecture is most fit for a typical architecture of ARM7. VLSI area, cycle delay time and execution cycle number is the index of an efficient design and the final multiplier was designed on these indexes. To verify the operation of embedded multiplier, it was simulated with various audio algorithms.

• The KIPS Transactions:PartA
• /
• v.9A no.3
• /
• pp.281-286
• /
• 2002

In this paper we, implement LSB-first digit-serial systolic multiplier for computing modular multiplication $A({\times})B$mod G ({\times})in finite fields GF $(2^m)$. If input data come in continuously, the implemented multiplier can produce multiplication results at a rate of one every [m/L] clock cycles, where L is the selected digit size. The analysis results show that the proposed architecture leads to a reduction of computational delay time and it has more simple structure than existing digit-serial systolic multiplier. Furthermore, since the propose architecture has the features of regularity, modularity, and unidirectional data flow, it shows good extension characteristics with respect to m and L.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.41 no.12
• /
• pp.1844-1850
• /
• 2016

The bilateral filter can reduce the noise while preserving details computing the filtering output at each pixels as the average of neighboring pixels. In this paper, we propose a real-time system based on window division. Overall performance is increased due to the parallel architectures which computes five rows in the kernel window simultaneously but with pipelined scheduling. We consider the tradeoff between the filter performance and the hardware cost and the bit allocation has been determined by PSNR analysis. The proposed architecture is designed with verilogHDL and synthesized using Dongbu Hitek 110nm standard cell library. The proposed architecture shows 416Mpixels/s (397fps) of throughput at 416MHz of operating frequency with 132K gates.