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A Study on Multiplier Architectures Optimized for 32-bit RISC Processor with 3-Stage Pipeline  

정근영 (부산대학교 전자공학과)
박주성 (부산대학교 전자공학과)
김석찬 (부산대학교 전자공학과)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.41, no.11, 2004 , pp. 123-130 More about this Journal
Abstract
This paper describes a multiplier architecture optimized for 32 bit RISC processor with 3-stage pipeline. The multiplier of ARM7, the target processor, is variably carried out on the execution stage of pipeline within 7 cycles. The included multiplier employs a modified Booth's algerian to produce 64 bit multiplication and addition product and it has 6 separate instructions. We analyzed several multiplication algorithm such as radix4-32${\times}$8, radix4-32${\times}$16 and radix8-32${\times}$32 to decide which multiplication architecture is most fit for a typical architecture of ARM7. VLSI area, cycle delay time and execution cycle number is the index of an efficient design and the final multiplier was designed on these indexes. To verify the operation of embedded multiplier, it was simulated with various audio algorithms.
Keywords
Multiplier; RISC; ARM7; Booth;
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