1 |
S. G. Smith and R.W.Morgan, 'Generic ASIC architecture for high-performance integer arithmetic realization,' Proc. of IEEE int. conf., computer design, 1989
|
2 |
K. C. Chang, Digital Systems Design with VHDL and Synthesis, IEEE Computer Society Press, 1999
|
3 |
http://www.synopsys.com
|
4 |
U. Meyer-Baese, Digital Signal Processing with Field Programmable Gate Arrays, Springer, 2001
|
5 |
J. J. Lee and G. Y. Song, 'Implementation of the Super-Systolic Array for Convolution,' ASP-DAC 2003, pp. 491-494, 2003
DOI
|
6 |
S. Nayak, and P. Meher, 'High throughput VLSI implementation of discrete orthogonal transforms using bit-level vector-matrix multiplier,' IEEE Trans. Circuits Syst. II, Analog Digital Signal Process., vol. 46, (5), pp. 655-658, 1999
DOI
ScienceOn
|
7 |
S. Y. Kung, 'On Supercomputing with Systolic /Wavefront Array processors,' IEEE computer, vol. 72, no. 7, 1984
|
8 |
K. T. Johnson, A. R. Hurson, 'General Purpose Systolic Arrays,' IEEE Computers, pp. 20-31, Novemver 1993
DOI
ScienceOn
|
9 |
J. Mccanny, J. Mcwhirter, and S. Y. Kung 'The use of data dependence graphs in the design of bit-level systolic arrays,' IEEE Trans. Acoust., Speech., Signal Process., vol. 18, pp. 787-793, 1990
DOI
ScienceOn
|
10 |
R. S. Grover, W. Chang and Q. Li, 'A comparison of FPGA implementation of two's complement bit-level and word-level matrix multiplier,' FPGA 2001, pp. 223, 2001
|
11 |
S. S. Nayak, 'Bit-level systolic implementation of 1D and 2D discrete wavelet transform.' IEE Proc. of Circuits, Devices and Systems, vol. 152, pp. 25-32, 2005
DOI
ScienceOn
|
12 |
S. Y. Kung, VLSI Array Processors, Prentice Hall, 1988
|
13 |
H. T. Kung, 'Why Systolic Architectures?,' IEEE Computer vol 15, no. 1, pp. 37-46, 1982
|
14 |
H. T. Kung and C.E.Leiserson, 'Systolic Arrays (for VLSI),' Sparse Matrix Proc., Academic Press, Orland, pp. 256-282, 1979
|