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http://dx.doi.org/10.7840/kics.2016.41.12.1844

Hardware Design of Bilateral Filter Based on Window Division  

Hyun, Yongho (Department of Information, Communication, and Electronic Engineering, The Catholic University of Korea)
Park, Taegeun (Department of Information, Communication, and Electronic Engineering, The Catholic University of Korea)
Publication Information
The Journal of Korean Institute of Communications and Information Sciences / v.41, no.12, 2016 , pp. 1844-1850 More about this Journal
Abstract
The bilateral filter can reduce the noise while preserving details computing the filtering output at each pixels as the average of neighboring pixels. In this paper, we propose a real-time system based on window division. Overall performance is increased due to the parallel architectures which computes five rows in the kernel window simultaneously but with pipelined scheduling. We consider the tradeoff between the filter performance and the hardware cost and the bit allocation has been determined by PSNR analysis. The proposed architecture is designed with verilogHDL and synthesized using Dongbu Hitek 110nm standard cell library. The proposed architecture shows 416Mpixels/s (397fps) of throughput at 416MHz of operating frequency with 132K gates.
Keywords
bilateral filter; edge preserving; VLSI architecture; pipelining; realtime system;
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