• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.1
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• pp.149-155
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• 2015

This paper proposes 5-MS/s 10-bit digital-to-analog converter(DAC) with the improved linearity. The proposed DAC consists of a 10-bit R-2R-based DAC, an output buffer using a differential voltage amplifier with rail-to-rail input range, and a band-gap reference circuit for the bias voltage. The linearity of the 10-bit R-2R DAC is improved as the resistor of 2R is implemented by including the turn-on resistance of an inverter for a switch. The output voltage range of the DAC is determined to be $2/3{\times}VDD$ from an rail-to-rail output voltage range of the R-2R DAC using a differential voltage amplifier in the output buffer. The proposed DAC is implemented using a 1-poly 8-metal 130nm CMOS process with 1.2-V supply. The measured dynamic performance of the implemented DAC are the ENOB of 9.4 bit, SNDR of 58 dB, and SFDR of 63 dBc. The measured DNL and INL are less than +/-0.35 LSB. The area and power consumption of DAC are $642.9{\times}366.6{\mu}m^2$ and 2.95 mW, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.7
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• pp.1227-1234
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• 2008

In this paper is designed a 256-bit synchronous OTP(one-time programmable) memory required in application fields such as automobile appliance power ICs, display ICs, and CMOS image sensors. A 256-bit synchronous memory cell consists of NMOS capacitor as antifuse and access transistor without a high-voltage blocking transistor. A gate bias voltage circuit for the additional blocking transistor is removed since logic supply voltage VDD(=1.5V) and external program voltage VPPE(=5.5V) are used instead of conventional three supply voltages. And loading current of cell to be programmed increases according to RON(on resistance) of the antifuse and process variation in case of the voltage driving without current constraint in programming. Therefore, there is a problem that program voltage can be increased relatively due to resistive voltage drop on supply voltage VPP. And so loading current can be made to flow constantly by using the current driving method instead of the voltage driving counterpart in programming. Therefore, program voltage VPP can be lowered from 5.9V to 5.5V when measurement is done on the manufactured wafer. And the sens amplifier circuit is simplified by using the sens amplifier of clocked inverter type instead of the conventional current sent amplifier. The synchronous OTP of 256 bits is designed with Magnachip $0.13{\mu}m$ CMOS process. The layout area if $298.4{\times}314{\mu}m2$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.12
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• pp.2366-2373
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• 2007

In this paper, a low-power and small-area asynchronous 1 kilobit EEPROM for passive UHF RFID tag chips is designed with $0.18{\mu}m$ EEPROM cells. As small area solutions, command and address buffers are removed since we design asynchronous I/O interface and data output buffer is also removed by using separate I/O. To supply stably high voltages VPP and VPPL used in the cell array from low voltage VDD, Dickson charge pump is designed with schottky diodes instead of a PN junction diodes. On that account, we can decrease the number of stages of the charge pump, which can decrease layout area of charge pump. As a low-power solution, we can reduce write current by using the proposed VPPL power switching circuit which selects each needed voltage at either program or write mode. A test chip of asynchronous 1 kilobit EEPROM is fabricated, and its layout area is $554.8{\times}306.9{\mu}m2$., 11% smaller than its synchronous counterpart.

• Journal of IKEEE
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• v.26 no.3
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• pp.422-429
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• 2022

A light sensor chip requires a small capacity eFuse (electrical fuse) OTP (One-Time Programmable) memory IP (Intellectual Property) to trim analog circuits or set initial values of digital registers. In this paper, 128-bit eFuse OTP IP is designed using only 3.3V MV (Medium Voltage) devices without using 1.8V LV (Low-Voltage) logic devices. The eFuse OTP IP designed with 3.3V single MOS devices can reduce a total process cost of three masks which are the gate oxide mask of a 1.8V LV device and the LDD implant masks of NMOS and PMOS. And since the 1.8V voltage regulator circuit is not required, the size of the illuminance sensor chip can be reduced. In addition, in order to reduce the number of package pins of the illumination sensor chip, the VPGM voltage, which is a program voltage, is applied through the VPGM pad during wafer test, and the VDD voltage is applied through the PMOS power switching circuit after packaging, so that the number of package pins can be reduced.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.905-908
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• 2005

본 논문에서는 class AB opamp 를 채용한 384kHz differential PWM 신호를 입력으로 하는 2-channel stereo audio amplifier 블록을 공급전압 3.3V 조건에서 SMIC 0.18um thick oxide 기술을 이용하여 설계한다. 여기서 class AB opamp 는 공정 변화에 따른 quiescent current가 변하는 것을 최소화하기 위하여 adaptive load 를 사용하며, 전체적으로는 3 차 Butterworth lowpass filter 와 differential-to-single converter 로 구성된 2 개의 audio amplifier 와 출력전압이 ${\frac{1}{2}}Vdd$ 인 common output 블록으로 구성된다. 이러한 설계를 통하여 32ohm 의 저항 load 를 구동할 수 있는 -60dB THD, 전체 quiescent current 2mA 대인 CMOS class AB stereo audio amplifier 를 구현하였다.

• ETRI Journal
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• v.30 no.3
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• pp.347-354
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• 2008

In this paper, the design of a low-power 512-bit synchronous EEPROM for a passive UHF RFID tag chip is presented. We apply low-power schemes, such as dual power supply voltage (VDD=1.5 V and VDDP=2.5 V), clocked inverter sensing, voltage-up converter, I/O interface, and Dickson charge pump using Schottky diode. An EEPROM is fabricated with the 0.25 ${\mu}m$ EEPROM process. Power dissipation is 32.78 ${\mu}W$ in the read cycle and 78.05 ${\mu}W$ in the write cycle. The layout size is 449.3 ${\mu}m$ ${\times}$ 480.67 ${\mu}m$.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.10
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• pp.3905-3910
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• 2010

In this paper, a 3rd-order Chebyshev current-mode filter in 1.8V-$0.18{\mu}m$ CMOS parameter is designed. The core circuit of the current-mode filter is composed with the proposed voltage-controlled frequency tunable current-mode integrator. Using the proposed current-mode integrator, the cutoff frequency of the filter can be controlled and also total power consumption can be reduced. HSPICE simulation results show the cutoff frequency of the filter is controlled between 1.2MHz and 10.1MHz, and the power consumption is 2.85mW at Vdd=1.8V.

• Journal of Chest Surgery
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• v.17 no.3
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• pp.356-361
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• 1984

During the period from January 1982 to June 1984 we implanted permanent pacemakers in 18 patients who received open heart surgery at Yonsei University Hospital. 1.In 11 patients, open heart surgery was performed at Yonsei University Hospital and new surgical induced heart blocks were developed and implantations of permanent pacemaker were done. 2.Total 1035 open heart surgeries were done and implantations of pacemaker were performed in 11 cases. [1.06%]. After total correction of TOF [215 cases] implantations of pacemaker were done in 3 cases. [1.4%] Implantations of pacemaker were 0.37% after VSD repair, 0.78% after ASD repair, 5.9% after ECD repair, 0.48% after MVR and 2.0% after AVR. 3.Causes were complete A-V block, sick sinus syndrome and A-V dissociation. 4.Heart blocks were developed immediately after bypass stop in 8 patients. 5.Implantations of pacemaker were done at more than 2 weeks after open heart surgery. 6.Local anesthesia was done in adult and general anesthesia in infants. Locations of pulse generator were subxiphoid, subcostal & subclavian. Position of pulse generator was between subcutaneous fat layer and muscle layer. 7.Types of pulse generator were VVI, VDD and AAI. 8.The postoperative complications included infection, pacing failure, sensing failure and lead dislodgment.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.26 no.6
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• pp.87-93
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• 2012

In this paper, we propose an analog-to-digital converter to set the address of a I2C slave chip. The proposed scheme converts a fixed voltage between 0 and VDD to the digital value which can be used as the address of the slave chip. The rising time and the falling time are measured with digital counter in a serially connected RC circuit, while the circuit is being charged and discharged with the voltage to be measured. The ratio of the two measured values is used to get the corresponding digital value. This scheme gives a strong point which is to be implementable all the parts except comparator using digital logic. Although the method utilizes RC circuit, it has no relation with the RC value if the quantization error is disregarded. Experimental result shows that the proposed scheme gives 32-level resolution thus it can be used to configure the address of the I2C slave chip.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.10
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• pp.2123-2135
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• 1997

In this paepr, we consider resistive shorts on drain-source, drain-gate, and gate-source as well as opens in MOSFETs included in typical memory cell of VLSI SRAM. Behavior of memeory is observed by analyzing voltage at storage nodes of memeory and IDDQ(quiescent power supply current) through PSPICE simulation. Using this behavioral analysis, an effective testing algorithm of complexity O(N) which can be applied to both functional testing and IDDQ testing simultaeously is proposed. Built-In Self Test(BIST) circuit which detects faults in memories and Built-In Current Sensor(BICS) which monitors the power supply bus for abnormalities in quescent current are developed and imprlemented to improve the quality and efficiency of testing. Implemented BIST and BICS circuits can detect locations of faults and defects in order to repair faulty memories.