• Proceedings of the Korea Multimedia Society Conference
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• 2002.05c
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• pp.1-5
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• 2002

본 논문에서는 UART(Universal Asynchronous Receiver-Transmitter)를 soft IP(Intellectual Property) 모듈 형태로써 VLSI 설계과정을 통하여 구현하였다. 이 모듈은 현재 각종 통신 디바이스에서 최하 말단에서 직렬 데이터를 시스템으로 받아들이거나 병렬 데이터를 직렬 라인에 실어 보내는 중요한 역할을 담당한다. 본 연구에서 설계한 UART는 간단한 모듈 형태로 제작되어 있어 Verilog-HDL을 사용하여 직렬 송ㆍ수신을 필요로 하는 시스템에 내장되어 사용될 수 있다. 본 논문에서는 설계 순서에 따라 UART를 설계하고 Simulation을 하고 Synopsys Tool을 사용하여 Compile 과 Synthesis 후 Gate Area 와 Belay를 검출해 내었다. 합성결과 0.25$\mu$m 공정의 CMOS Cell Library를 사용하였을 경우 전체 면적은 1,013 gate가 나왔다. 본 논문에서 설계한 UART의 최장경로가 최대 4.12ns로 나타났으며, 최대 동작 클럭 주파수는 200MHz 로써 150Mbps 이상의 전송 속도를 가진다.

• Journal of information and communication convergence engineering
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• v.14 no.2
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• pp.115-121
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• 2016

Currently there is a lack of literature on SPICE-level models of double-gate (DG) tunnel field-effect transistors (TFETs). A DG TFET compact model is presented in this work that is used to develop a SPICE model for DG TFETs implemented with Verilog-A language. The compact modeling approach presented in this work integrates several issues in previously published compact models including ambiguity about the use of tunneling parameters A_k and B_k, and the use of a universal equation for calculating the surface potential of DG TFETs in all regimes of operation to deliver a general SPICE modeling procedure for DG TFETs. The SPICE model of DG TFET captures the drain current-gate voltage (I_ds-V_gs) characteristics of DG TFET reasonably well and offers a definite computational advantage over TCAD. The general SPICE modeling procedure presented here could be used to develop SPICE models for any combination of structural parameters of DG TFETs.

• The Journal of the Acoustical Society of Korea
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• v.39 no.5
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• pp.435-440
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• 2020

Single-beam acoustic tweezers that are capable of manipulating micron-size particles in a non-contact manner have been used in many biological and biomedical applications. Current single-beam acoustic tweezer systems developed for in vitro experiments consist of a function generator and a power amplifier, thus the system is bulky and expensive. This configuration would not be suitable for in vivo and clinical applications. Thus, in this paper, we present a portable single-beam acoustic tweezer system and its performances of trapping and manipulating micron-size objects. The developed system consists of an Field Programmable Gate Array (FPGA) chip and two pulsers, and parameters such as center frequency and pulse duration were controlled by a Personal Computer (PC) via a USB (Universal Serial Bus) interface in real-time. It was shown that the system was capable of generating the transmitting pulse up to 20 MHz, and producing sufficient intensity to trap microparticles and cells. The performance of the system was evaluated by trapping and manipulating 40 ㎛ and 90 ㎛ in diameter polystyrene particles.

• ETRI Journal
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• v.25 no.5
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• pp.328-336
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• 2003

Bluetooth is a specification for short-range wireless communication using the 2.4 GHz ISM band. It emphasizes low complexity, low power, and low cost. This paper describes an area-efficient digital baseband module for wireless technology. For area-efficiency, we carefully consider hardware and software partitioning. We implement complex control tasks of the Bluetooth baseband layer protocols in software running on an embedded microcontroller. Hardware-efficient functions, such as low-level bitstream link control; host controller interfaces (HCIs), such as universal asynchronous receiver transmitter (UART) and universal serial bus (USB)interfaces; and audio Codec are performed by dedicated hardware blocks. Furthermore, we eliminate FIFOs for data buffering between hardware functional units. The design is done using fully synthesizable Verilog HDL to enhance the portability between process technologies so that our module can be easily integrated as an intellectual property core no system-on-a-chip (SoC) ASICs. A field programmable gate array (FPGA) prototype of this module was tested for functional verification and realtime operation of file and bitstream transfers between PCs. The module was fabricated in a $0.25-{\mu}m$ CMOS technology, the core size of which was only 2.79 $mm{\times}2.80mm$.

• Journal of the Korean Institute of Telematics and Electronics
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• v.17 no.6
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• pp.51-57
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• 1980

Any switching function can be constructed with universal building block of MAND gate. Threelevel AND-NOT logic networks with only true inputs are called TANT networks. Systematic approach to TANT minimization starts from the UF type minterm with the smallest subscript and ends when UF type minterms are all covered. Optinal PEI is composed of CPPI or EPPi without C-C table. The algorithm in this work is usful in solving TANT optimization porblem of four or five variables by hand solution. When variable are six or more, it is required to be solved by computer, A CAD software package of this algorithm with FORTRAN IV language is made to solve such problems.

• Journal of information and communication convergence engineering
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• v.9 no.4
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• pp.435-440
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• 2011

This paper propose the method of constructing the highly efficiency adder and multiplier systems over finite fields. The addition arithmetic operation over finite field is simple comparatively because that addition arithmetic operation is analyzed by each digit modP summation independently. But in case of multiplication arithmetic operation, we generate maximum k=2m-2 degree of ${\alpha}^k$ terms, therefore we decrease k into m-1 degree using irreducible primitive polynomial. We propose two method of control signal generation for the purpose of performing above decrease process. One method is the combinational logic expression and the other method is universal signal generation. The proposed method of constructing the highly adder/multiplier systems is as following. First of all, we obtain algorithms for addition and multiplication arithmetic operation based on the mathematical properties over finite fields, next we construct basic cell of A-cell and M-cell using T-gate and modP cyclic gate. Finally we construct adder module and multiplier module over finite fields after synthesizing ${\alpha}^k$ generation module and control signal CSt generation module with A-cell and M-cell. Next, we constructing the arithmetic operation unit over finite fields. Then, we propose the future research and prospects.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.21 no.2
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• pp.214-220
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• 2012

About 12 million people of the mobility handicapped were increased by the end of 2009 year. Universal design concept has been implemented in developed countries. Since 2004 low-floor buses are in Korea. In this study, there is no provision for mobility handicapped and small buses that can be comfortable riding car ramp design presented. The gate of a small buses lowered height of 200mm. Install the ramp in the center of the ramp by an air cylinder moves from side to side. The slope of the ramp was controlled by a hinge. Air cylinder thin type applicable in the narrow space of the slide cylinder was used.

• Journal of Power Electronics
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• v.14 no.6
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• pp.1139-1146
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• 2014

Digital signal processor (DSP) and field programmable gate array (FPGA) based concentrated control systems are designed for implementing CPS-SPWM strategies. The self-defined universal asynchronous receiver/transmitter (UART) protocol is used for communication between a master controller and an individual module controller via high speed links. Aimed at undesired pulse competition, this paper analyzes its generation mechanism and presents a new method for eliminating competition pulses with no time delay. Finally, the proposed concentrated controller is applied to a 10kV/10MVar distribution static synchronous compensator (DSTATCOM) industrial prototype. Experimental results show the accuracy and reliability of the concentrated controller, and verify the superiority of the proposed elimination method for competition pulses.

• Proceedings of the Korea Information Processing Society Conference
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• 2002.11c
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• pp.1713-1716
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• 2002

HyREX는 연구용 프로토타입 XML 하이퍼미디어 문서 검색시스템으로 다국어를 지원하고 있다. HyREX는 검색을 위한 효율적인 접근 경로들을 처리하는 물리적 계층 HyPath와 질의어를 처리하는 논리적 계층 XIRQL 그리고 사용자 인터페이스인 HyGate 계층으로 이루어져 있다. 이 연구에서는 영어와 독일어 등의 검색을 지원하는 기존의 HyREX 시스템을 한글 XML 문서 검색시스템으로 확장하기 위해 먼저 한글 데이터타입을 위한 클래스를 구현하였다. 앞으로 한글 XML 문서 검색에서 정확율과 재현율을 향상하기 위해 각 문서의 인덱스에 대해 $tf{\cdot}idf$ 공식을 이용하여 가중치를 부여하고 이를 개발하고자 한다.

• Journal of the Korean Magnetics Society
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• v.17 no.1
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• pp.6-9
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• 2007

The generation of entanglement is a very important subject in the quantum computer. Here we suggest the method that generates entanglement between two spin-1/2 particles by using the third moving spin-1/2 particle. We use the $F\"{o}rster$ interaction and the exchange interaction to make the entangled state.