• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.911-913
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• 1999

Shallow Trench Isolation (STI) has become the most promising isolation scheme for ULSI applications. The stress of STI structure is one of several factors to degrade characteristics of a device. The stress contours or STI structure vary with the trench depth. Isolation characteristics of STI was analyzed as the depth of trench varied. And transistor characteristics was compared. Isolation punch-through voltage for n$^{＋}$ to pwell and p$^{＋}$ to nwell increased as trench depth increased. n$^{＋}$ to pwell leakage current had nothing to do with trench depth but n$^{＋}$ to pwell leakage current decreased as trench depth increased. In the case of transistor characteristics, short channel effect was independent on trench depth and inverse narrow width effect was greater for deeper trenches. Therefore in order to achieve stable device, it is important to minimize stress by optimizing trench depth.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.3
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• pp.120-130
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• 1998

In this study, we implemented a scanning capacitance decimicron micorscope(SCdM) which scans a surface of the object mechanically in two or two point five dimensions with a stylus of size 0.2.mu.m. X-Y stage and stylus driving method are used as the scanning method, and VHD disk plate and IC chip are used as the object. Experimenal resutl of these object show that SCdM obtain 0.1.mu.m resolution power which exceeds that of optical microscope, and this microscope will be used as a powerful tool for inspecting ULSI pattern or biological data as a decimicron mcirocope which zoom a function of optical microscope and guide STM. The experimental system is composed of a VHD video disk method which captures the capacitance changes of the video disk suface and converts it into video signal.

• Journal of the Semiconductor & Display Technology
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• v.14 no.2
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• pp.41-45
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• 2015

From 20nm technology node, the finFET has become standard device for ULSI's. However, the finFET process made stacking gate non-volatile memory obsolete. Some reported capacitor-less DRAM structure by utilizing the FBE. We present possible non-volatile memory device structure similar to the dual gate MOSFET. One of the gates is left floating. Since body of the finFET is only 40nm thick, control gate bias can make electron tunneling through the floating gate oxide which sits across the body. For programming, gate is biased to accumulation mode with few volts. Simulation results show that the programming electron current flows at the interface between floating gate oxide and the body. It also shows that the magnitude of the programming current can be easily controlled by the drain voltage. Injected electrons at the floating gate act similar to the body bias which changes the threshold voltage of the device.

• ETRI Journal
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• v.20 no.2
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• pp.241-249
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• 1998

The structure and electrical characteristics of metal-ferroelectric-semiconductor FET(MFSFET) for a single transistor memory are presented. The MFSFET was comprised of polysilicon islands as source/drain electrodes and $BaMgF_4$ film as a gate dielectric. The polysilicon source and drain were built-up prior to the formation of the ferroelectric film to suppress a degradation of the film due to high thermal cycles. From the MFS capacitor, the remnant polarization and coercive field were measured to be about $0.6{\mu}C/cm^2$ and 100 kV/cm, respectively. The fabricated MFSFETs also showed good hysteretic I-V curves, while the current levels disperse probably due to film cracking or bad adhesion between the film and the Al electrode.

• Journal of the Microelectronics and Packaging Society
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• v.11 no.4 s.33
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• pp.75-80
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• 2004

In copper metallization, resistivity of copper seed layer is very important. Conventionally MOCVD has been used for this purpose however electroless copper plating is simple process and the resistivity of copper deposit is less than that of copper prepared by MOCVD. In this study electroless copper plating was conducted on different substrate to find optimum conditions of electroless copper plating for electronic applications. To find optimum conditions, the effects and selectivity of activation method on several substrates were investigated. The effects of copper bath composition on morphology were investigated. The effects of pH and stabilizer on deposition rate were also investigated. The optimum pH of the bath was 12 with addition of stabilizer. The resistivity of copper was decreased with addition of stabilizer and alter heat treatment.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.8
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• pp.8-21
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• 1997

In this paper, we consider resistive shorts on gate-source, gate-drain, and drain-source as well as opens in MOS FETs included in typical memory cell of VLSI SRAM and analyze behavior of memory by using PSPICE simulation. Using conventional fault models and this behavioral analysis, we propose linear testing algorithm of complexity O(N) which can be applied to both functional testing and IDDQ (quiescent power supply current) testing simultaneously to improve functionality and reliability of memory. Finally, we implement BIST (built-in self tsst) circuit and BICS(built-in current sensor), which are embedded on memory chip, to carry out functional testing efficiently and to detect various defects at high-speed respectively.

• Proceedings of the Materials Research Society of Korea Conference
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• 2010.05a
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• pp.48.1-48.1
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• 2010

Cu has been used for metallic interconnects in ULSI applications because of its lower resistivity according to the scaling down of semiconductor devices. The resistivity of Cu lines will affect the RC delay and will limit signal propagation in integrated circuits. In this study, we investigated the characteristics of electroplated Cu films according to the variation of concentration of organic additives. The plating electrolyte composed of $CuSO_4{\cdot}5H_2O$, $H_2SO_4$ and HCl, was fixed. The sheet resistance was measured with a four-point probe and the material properties were investigated with XRD (X-ray Diffraction), AFM (Atomic Force Microscope), FE-SEM (Field Emission Scanning Electron Microscope) and XPS (X-ray Photoelectron Spectroscopy). From these experimental results, we found that the organic additives play an important role in formation of Cu film with lower resistivity by EPD.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.428-431
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• 2003

In this paper, the stress induced leakage currents of thin silicon oxides is investigated in the ULSI implementation with nano structure transistors. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The stress and transient currents were due to the charging and discharging of traps generated by high stress voltage in the silicon oxides. The transient current was caused by the tunnel charging and discharging of the stress generated traps nearby two interfaces. The stress induced leakage current will affect data retention in electrically erasable programmable read only memories. The oxide current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between $113.4{\AA}$ and $814{\AA}$, which have the gate area 10-3cm2. The stress induced leakage currents will affect data retention and the stress current, transient current is used to estimate to fundamental limitations on oxide thicknesses.

• Proceedings of the Korean Information Science Society Conference
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• 1998.10c
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• pp.674-676
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• 1998

소자가 sub-quarter um급으로 축소됨에 따라 STI(Shallow Trench Isolation) 기술은 고 집적도의 ULSI 구현에 있어서 중요한 격리 방법으로 많이 사용되고 있다. 현재의 STI 기술은 주로 실리콘 기판을 식각 후 절연물질로 빈 공백이 없이 채우는 (void-free gap filling) 방법 [1,2]과 절연물질을 다시 표면 근처까지 CMP(Chemical Mechnical Polishing)로 etchback하여 평탄화를 하는 방법이 주요한 기술이 되고 있다. 또한 STI 구조로된 격리구조에서 만들어진 MOSFET의 전기적인 특성은 트랜치 격리의 상부 부분의 형태와 gap-filling 물질에 따라 큰 영향을 받게된다. 따라서 본 논문에서는 STI 구조로 만들어진 격리 구조에서 MOSFET의 hump 특성에 관해 연구하였다. 그 결과 hump는 STI 모서리에서 필드 옥사이드의 recess에 의한 모서리 부분에서의 전계 집중과 boron의 segration에 기인한 농도 감소로 인해 hump가 발생하는 것으로 나타났다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.6
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• pp.465-470
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• 2003

The chemical mechanical polishing (CMP) process has been widely used for the global planarization of multi-layer structures in semiconductor manufacturing. The CMP process can be optimized by several parameters such as equipment, consumables (pad, backing film and slurry), process variables and post-CMP cleaning. However, the COO(cost of ownership) is very high, because of high consumable cost. Especially, among the consumables, the slurry dominates more than 40 %. In this paper, we have studied the CMP characteristics of diluted silica slurry by adding of raw alumina abrasives and annealed alumina abrasives. As an experimental result, we obtained the comparable slurry characteristics compared with original silica slurry in the view-point of high removal rate and low non-uniformity. Therefore, we can reduce the cost of consumables(COC) of CMP process for ULSI applications.