• Journal of Power Electronics
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• v.16 no.1
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• pp.362-373
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• 2016

The on-line measurement of high-power IGBT collector current is important for the hierarchical control and short-circuit and overcurrent protection of its driver and the sensorless control of the converter. The conventional on-line measurement methods for IGBT collector current are not suitable for engineering measurement due to their large-size, high-cost, low-efficiency sensors, current transformers or dividers, etc. Based on the gate driver, this paper has proposed a current measuring circuit for IGBT collector current. The circuit is used to conduct non-intervention on-line measurement of IGBT collector current by detecting the voltage drop of the IGBT power emitter and the auxiliary emitter terminals. A theoretical analysis verifies the feasibility of this circuit. The circuit adopts an operational amplifier for impedance isolation to prevent the measuring circuit from affecting the dynamic performance of the IGBT. Due to using the scheme for integration first and amplification afterwards, the difficult problem of achieving high accuracy in the transient-state and on-state measurement of the voltage between the terminals of IGBT power emitter and the auxiliary emitter (u_Ee) has been solved. This is impossible for a conventional detector. On this basis, the adoption of a two-stage operational amplifier can better meet the requirements of high bandwidth measurement under the conditions of a small signal with a large gain. Finally, various experiments have been carried out under the conditions of several typical loads (resistance-inductance load, resistance load and inductance load), different IGBT junction temperatures, soft short-circuits and hard short-circuits for the on-line measurement of IGBT collector current. This is aided by the capacitor voltage which is the integration result of the voltage uEe. The results show that the proposed method of measuring IGBT collector current is feasible and effective.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.629-631
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• 2004

The proposed output buffer is presented for driving large-size LCD panels. This output buffer is designed by adding some simple circuitry to the conventional two-stage operational amplifier. The proposed circuit is simulated in a high-voltage 0.35um CMOS process with HSPICE. The simulated result is more improved settling time than that of conventional one.

• ETRI Journal
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• v.28 no.4
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• pp.495-501
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• 2006

This paper presents a new CMOS fully-differential second-generation current conveyor (FDCCII). The proposed FDCCII is based on a fully-differential difference transconductor as an input stage and two class AB output stages. Besides the proposed FDCCII circuit operating at a supply voltage of ${\pm}1.5\;V$, it has a total standby current of $380\;{\mu}A$. The applications of the FDCCII to realize a variable gain amplifier, fully-differential integrator, and fully-differential second-order bandpass filter are given. The proposed FDCII and its applications are simulated using CMOS $0.35\;{\mu}m$ technology.

• Proceedings of the Korean Information Science Society Conference
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• 2004.04a
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• pp.931-933
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• 2004

In a SoC environment, asynchronous design techniques offer solutions for problems of synchronous design techniques. Asynchronous FIFOs have the advantages of easier interconnection methods and higher throughput than synchronous ones. Low latency and high throughput are two imp ortant standards in asynchronous FIFOs. We present low latency asynchronous FIFO in the paper, which optimizes GasP[6]. Pre-layout of HSPICE simulations of a 8-stage FIFO on 1-bit datapath using Anam's 0.25$\mu\textrm{m}$ technology indicates 17% lower latency than GasP.

• ETRI Journal
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• v.36 no.3
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• pp.498-501
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• 2014

A C-band 50 W high-power microwave monolithic integrated circuit amplifier for use in a phased-array radar system was designed and fabricated using commercial $0.25{\mu}m$ AlGaN/GaN technology. This two-stage amplifier can achieve a saturated output power of 50 W with higher than 35% power-added efficiency and 22 dB small-signal gain over a frequency range of 5.5 GHz to 6.2 GHz. With a compact $14.82mm^2$ chip area, an output power density of $3.2W/mm^2$ is demonstrated.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.650-656
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• 2016

Voltage controlled oscillator (VCO) is widely used circuit component in high-performance microprocessors and modern communication systems as a frequency source. In present work, VCO designs using the different combination of NAND gates with three transistors and CMOS inverter are reported. Three, five and seven stages ring VCO circuits are designed. Coarse and fine tuning have been done using two different supply sources. The frequency with coarse tuning varies from 3.31 GHz to 5.60 GHz in three stages, 1.77 GHz to 3.26 GHz in five stages and 1.27 GHz to 2.32 GHz in seven stages VCO respectively. Moreover, for fine tuning frequency varies from 3.70 GHz to 3.94 GHz in three stages, 2.04 GHz to 2.18 GHz in five stages and 1.43 GHz to 1.58 GHz in seven stages VCO respectively. Results of power consumption and phase noise for the VCO circuits are also been reported. Results of proposed VCO circuits have been compared with previously reported circuits and present circuit approach show significant improvement.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2003.11a
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• pp.113-117
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• 2003

This paper describes the design and the simulation results of the RF CMOS Class-E Power Amplifier for a 2.4GHz ISM band. This circuit is composed two connected amplifiers. where Class F amplifier drives Class E amplifier. The proposed circuit can reduce the total power dissipation of the driving stage and can work with higher efficiency. The power amplifier has been implemented in a standard $0.25{\mu}m$ CMOS technology and is shown to deliver 100mW output power to load with 41% power added efficiency(PAE) from a 2.5V supply.

• ETRI Journal
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• v.35 no.2
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• pp.226-233
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• 2013

This paper presents a two-stage power-efficient class-AB operational transconductance amplifier (OTA) based on an adaptive biasing circuit suited to low-power dissipation and low-voltage operation. The OTA shows significant improvements in driving capability and power dissipation owing to the novel adaptive biasing circuit. The OTA dissipates only $0.4{\mu}W$ from a supply voltage of ${\pm}0.6V$ and exhibits excellent high driving, which results in a slew rate improvement of more than 250 times that of the conventional class-AB amplifier. The design is fabricated using $0.18-{\mu}m$ CMOS technology.

• Proceedings of the IEEK Conference
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• 2003.11c
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• pp.335-339
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• 2003

This Paper describes the design and the simulation results of the RF CMOS Class-E Power Amplifier for a 2.4GHz ISM band. This circuit is composed two connected amplifiers. where Class F amplifier drives Class E amplifier. The proposed circuit can reduce the total power dissipation of the driving stage and can work with higher efficiency. The power amplifier has been implemented in a standard 0.25$\mu\textrm{m}$ CMOS technology and is shown to deliver 100mW output Power to load with 41％ power added efficiency(PAE) from a 2.5V supply.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.6
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• pp.1158-1165
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• 2004

This paper describes the design of a two stage 1V power supply SiGe Low Noise Amplifier operating at 5.25㎓ for 802.lla wireless LAN application. The achieved performance includes a gain of 17㏈, noise figure of 2.7㏈, reflection coefficient of 15㏈, IIP3 of -5㏈m, and 1-㏈ compression point of -14㏈m. The total power consumption of the circuit was 7㎽ including 0.5㎽ for the bias circuit.