• Title/Summary/Keyword: Transistors

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Simulation Study of a Large Area CMOS Image Sensor for X-ray DR Detector with Separate ROICs (센서-회로 분리형 엑스선 DR 검출기를 위한 대면적 CMOS 영상센서 모사 연구)

  • Kim, Myung Soo;Kim, Hyoungtak;Kang, Dong-uk;Yoo, Hyun Jun;Cho, Minsik;Lee, Dae Hee;Bae, Jun Hyung;Kim, Jongyul;Kim, Hyunduk;Cho, Gyuseong
    • Journal of Radiation Industry
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    • v.6 no.1
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    • pp.31-40
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    • 2012
  • There are two methods to fabricate the readout electronic to a large-area CMOS image sensor (LACIS). One is to design and manufacture the sensor part and signal processing electronics in a single chip and the other is to integrate both parts with bump bonding or wire bonding after manufacturing both parts separately. The latter method has an advantage of the high yield because the optimized and specialized fabrication process can be chosen in designing and manufacturing each part. In this paper, LACIS chip, that is optimized design for the latter method of fabrication, is presented. The LACIS chip consists of a 3-TR pixel photodiode array, row driver (or called as a gate driver) circuit, and bonding pads to the external readout ICs. Among 4 types of the photodiode structure available in a standard CMOS process, $N_{photo}/P_{epi}$ type photodiode showed the highest quantum efficiency in the simulation study, though it requires one additional mask to control the doping concentration of $N_{photo}$ layer. The optimized channel widths and lengths of 3 pixel transistors are also determined by simulation. The select transistor is not significantly affected by channel length and width. But source follower transistor is strongly influenced by length and width. In row driver, to reduce signal time delay by high capacitance at output node, three stage inverter drivers are used. And channel width of the inverter driver increases gradually in each step. The sensor has very long metal wire that is about 170 mm. The repeater consisted of inverters is applied proper amount of pixel rows. It can help to reduce the long metal-line delay.

Understanding Interfacial Charge Transfer Nonlinearly Boosted by Localized States Coupling in Organic Transistors (Carbon Nano Tube 및 산화그래핀을 첨가한 폴리우레아 복합재 제조 및 그 화학적 특성 분석)

  • Kim, Hyeongtae;Lee, Jihyun;An, Woo-Jin;Park, Jun Hong
    • Journal of Adhesion and Interface
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    • v.22 no.4
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    • pp.136-143
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    • 2021
  • Polyurea has been investigated as a polymer matrix for composite materials because of its high mechanical strength. Although polyurea has a similar chemical structure to polyurethane, it has much higher strength and durability. In this study, the fabrication of polyurea composites reinforced with carbon nanotube (CNT) and graphene oxide (GO) is demonstrated to enhance the tensile strength of the glass fibers composite. Using FTIR and Raman spectroscopies, the chemical structures of polyurea, CNT, and GO are investigated. As a result, spectroscopy analysis reveals that the chemical structure of CNT, GO, and polyurea is maintained during the fabrication of the composite structure. Scanning electron microscopy reveals the uniform distribution of CNT and GO across the polyurea matrix. The reinforcement of 1 wt% CNT in polyurea enhances the tensile strength of CNT/polyurea composites. In contrast, the reinforcement of GO in polyurea induces the degradation of the tensile strength of GO/polyurea composites.

High Voltage β-Ga2O3 Power Metal-Oxide-Semiconductor Field-Effect Transistors (고전압 β-산화갈륨(β-Ga2O3) 전력 MOSFETs)

  • Mun, Jae-Kyoung;Cho, Kyujun;Chang, Woojin;Lee, Hyungseok;Bae, Sungbum;Kim, Jeongjin;Sung, Hokun
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.32 no.3
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    • pp.201-206
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    • 2019
  • This report constitutes the first demonstration in Korea of single-crystal lateral gallium oxide ($Ga_2O_3$) as a metal-oxide-semiconductor field-effect-transistor (MOSFET), with a breakdown voltage in excess of 480 V. A Si-doped channel layer was grown on a Fe-doped semi-insulating ${\beta}-Ga_2O_3$ (010) substrate by molecular beam epitaxy. The single-crystal substrate was grown by the edge-defined film-fed growth method and wafered to a size of $10{\times}15mm^2$. Although we fabricated several types of power devices using the same process, we only report the characterization of a finger-type MOSFET with a gate length ($L_g$) of $2{\mu}m$ and a gate-drain spacing ($L_{gd}$) of $5{\mu}m$. The MOSFET showed a favorable drain current modulation according to the gate voltage swing. A complete drain current pinch-off feature was also obtained for $V_{gs}<-6V$, and the three-terminal off-state breakdown voltage was over 482 V in a $L_{gd}=5{\mu}m$ device measured in Fluorinert ambient at $V_{gs}=-10V$. A low drain leakage current of 4.7 nA at the off-state led to a high on/off drain current ratio of approximately $5.3{\times}10^5$. These device characteristics indicate the promising potential of $Ga_2O_3$-based electrical devices for next-generation high-power device applications, such as electrical autonomous vehicles, railroads, photovoltaics, renewable energy, and industry.

A 0.2V DC/DC Boost Converter with Regulated Output for Thermoelectric Energy Harvesting (열전 에너지 하베스팅을 위한 안정화된 출력을 갖는 0.2V DC/DC 부스트 변환기)

  • Cho, Yong-hwan;Kang, Bo-kyung;Kim, Sun-hui;Yang, Min-Jae;Yoon, Eun-jung;Yu, Chong-gun
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2014.10a
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    • pp.565-568
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    • 2014
  • This paper presents a 0.2V DC/DC boost converter with regulated output for thermoelectric energy harvesting. To use low voltages from a thermoelectric device, a start-up circuit consisting of native NMOS transistors and resistors boosts an internal VDD, and the boosted VDD is used to operate the internal control block. When the VDD reaches a predefined value, a detector circuit makes the start-up block turn off to minimize current consumption. The final boosted VSTO is achieved by alternately operating the sub-boost converter for VDD and the main boost converter for VSTO according to the comparator outputs. When the VSTO reaches 2.4V, a buck converter starts to operate to generate a stabilized output VOUT. Simulation results shows that the designed converter generates a regulated 1.8V output from an input voltage of 0.2V, and its maximum power efficiency is 60%. The chip designed using a $0.35{\mu}m$ CMOS process occupies $1.1mm{\times}1.0mm$ including pads.

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Tuning Electrical Performances of Organic Charge Modulated Field-Effect Transistors Using Semiconductor/Dielectric Interfacial Controls (유기반도체와 절연체 계면제어를 통한 유기전하변조 트랜지스터의 전기적 특성 향상 연구)

  • Park, Eunyoung;Oh, Seungtaek;Lee, Hwa Sung
    • Journal of Adhesion and Interface
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    • v.23 no.2
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    • pp.53-58
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    • 2022
  • Here, the surface characteristics of the dielectric were controlled by introducing the self-assembled monolayers (SAMs) as the intermediate layers on the surface of the AlOx dielectric, and the electrical performances of the organic charge modulated transistor (OCMFET) were significantly improved. The organic intermediate layer was applied to control the surface energy of the AlOx gate dielectric acting as a capacitor plate between the control gate (CG) and the floating gate (FG). By applying the intermediate layers on the gate dielectric surface, and the field-effect mobility (μOCMFET) of the OCMFET devices could be efficiently controlled. We used the four kinds of SAM materials, octadecylphosphonic acid (ODPA), butylphosphonic acid (BPA), (3-bromopropyl)phosphonic acid (BPPA), and (3-aminopropyl)phosphonic acid (APPA), and each μOCMFET was measured at 0.73, 0.41, 0.34, and 0.15 cm2V-1s-1, respectively. The results could be suggested that the characteristics of each organic SAM intermediate layer, such as the length of the alkyl chain and the type of functionalized end-group, can control the electrical performances of OCMFET devices and be supported to find the optimized fabrication conditions, as an efficient sensing platform device.

Evaluation of Dynamic X-ray Imaging Sensor and Detector Composing of Multiple In-Ga-Zn-O Thin Film Transistors in a Pixel (픽셀내 다수의 산화물 박막트랜지스터로 구성된 동영상 엑스레이 영상센서와 디텍터에 대한 평가)

  • Seung Ik Jun;Bong Goo Lee
    • Journal of the Korean Society of Radiology
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    • v.17 no.3
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    • pp.359-365
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    • 2023
  • In order to satisfy the requirements of dynamic X-ray imaging with high frame rate and low image lag, minimizing parasitic capacitance in photodiode and overlapped electrodes in pixels is critically required. This study presents duoPIXTM dynamic X-ray imaging sensor composing of readout thin film transistor, reset thin film transistor and photodiode in a pixel. Furthermore, dynamic X-ray detector using duoPIXTM imaging sensor was manufactured and evaluated its X-ray imaging performances such as frame rate, sensitivity, noise, MTF and image lag. duoPIXTM dynamic X-ray detector has 150 × 150 mm2 imaging area, 73 um pixel pitch, 2048 × 2048 matrix resolution(4.2M pixels) and maximum 50 frames per second. By means of comparison with conventional dynamic X-ray detector, duoPIXTM dynamic X-ray detector showed overall better performances than conventional dynamic X-ray detector as shown in the previous study.

Growth of hexagonal Si epilayer on 4H-SiC substrate by mixed-source HVPE method (혼합 소스 HVPE 방법에 의한 4H-SiC 기판 위의 육각형 Si 에피층 성장)

  • Kyoung Hwa Kim;Seonwoo Park;Suhyun Mun;Hyung Soo Ahn;Jae Hak Lee;Min Yang;Young Tea Chun;Sam Nyung Yi;Won Jae Lee;Sang-Mo Koo;Suck-Whan Kim
    • Journal of the Korean Crystal Growth and Crystal Technology
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    • v.33 no.2
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    • pp.45-53
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    • 2023
  • The growth of Si on 4H-SiC substrate has a wide range of applications as a very useful material in power semiconductors, bipolar junction transistors and optoelectronics. However, it is considerably difficult to grow very fine crystalline Si on 4H-SiC owing to the lattice mismatch of approximately 20 % between Si and 4H-SiC. In this paper, we report the growth of a Si epilayer by an Al-related nanostructure cluster grown on a 4H-SiC substrate using a mixed-source hydride vapor phase epitaxy (HVPE) method. In order to grow hexagonal Si on the 4H-SIC substrate, we observed the process in which an Al-related nanostructure cluster was first formed and an epitaxial layer was formed by absorbing Si atoms. From the FE-SEM and Raman spectrum results of the Al-related nanostructure cluster and the hexagonal Si epitaxial layer, it was considered that the hexagonal Si epitaxial layer had different characteristics from the general cubic Si structure.

A 1280-RGB $\times$ 800-Dot Driver based on 1:12 MUX for 16M-Color LTPS TFT-LCD Displays (16M-Color LTPS TFT-LCD 디스플레이 응용을 위한 1:12 MUX 기반의 1280-RGB $\times$ 800-Dot 드라이버)

  • Kim, Cha-Dong;Han, Jae-Yeol;Kim, Yong-Woo;Song, Nam-Jin;Ha, Min-Woo;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.1
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    • pp.98-106
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    • 2009
  • This work proposes a 1280-RGB $\times$ 800-Dot 70.78mW 0.l3um CMOS LCD driver IC (LDI) for high-performance 16M-color low temperature poly silicon (LTPS) thin film transistor liquid crystal display (TFT-LCD) systems such as ultra mobile PC (UMPC) and mobile applications simultaneously requiring high resolution, low power, and small size at high speed. The proposed LDI optimizes power consumption and chip area at high resolution based on a resistor-string based architecture. The single column driver employing a 1:12 MUX architecture drives 12 channels simultaneously to minimize chip area. The implemented class-AB amplifier achieves a rail-to-rail operation with high gain and low power while minimizing the effect of offset and output deviations for high definition. The supply- and temperature-insensitive current reference is implemented on chip with a small number of MOS transistors. A slew enhancement technique applicable to next-generation source drivers, not implemented on this prototype chip, is proposed to reduce power consumption further. The prototype LDI implemented in a 0.13um CMOS technology demonstrates a measured settling time of source driver amplifiers within 1.016us and 1.072us during high-to-low and low-to-high transitions, respectively. The output voltage of source drivers shows a maximum deviation of 11mV. The LDI with an active die area of $12,203um{\times}1500um$ consumes 70.78mW at 1.5V/5.5V.

A 10b 50MS/s Low-Power Skinny-Type 0.13um CMOS ADC for CIS Applications (CIS 응용을 위해 제한된 폭을 가지는 10비트 50MS/s 저 전력 0.13um CMOS ADC)

  • Song, Jung-Eun;Hwang, Dong-Hyun;Hwang, Won-Seok;Kim, Kwang-Soo;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.48 no.5
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    • pp.25-33
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    • 2011
  • This work proposes a skinny-type 10b 50MS/s 0.13um CMOS three-step pipeline ADC for CIS applications. Analog circuits for CIS applications commonly employ a high supply voltage to acquire a sufficiently acceptable dynamic range, while digital circuits use a low supply voltage to minimize power consumption. The proposed ADC converts analog signals in a wide-swing range to low voltage-based digital data using both of the two supply voltages. An op-amp sharing technique employed in residue amplifiers properly controls currents depending on the amplification mode of each pipeline stage, optimizes the performance of op-amps, and improves the power efficiency. In three FLASH ADCs, the number of input stages are reduced in half by the interpolation technique while each comparator consists of only a latch with low kick-back noise based on pull-down switches to separate the input nodes and output nodes. Reference circuits achieve a required settling time only with on-chip low-power drivers and digital correction logic has two kinds of level shifter depending on signal-voltage levels to be processed. The prototype ADC in a 0.13um CMOS to support 0.35um thick-gate-oxide transistors demonstrates the measured DNL and INL within 0.42LSB and 1.19LSB, respectively. The ADC shows a maximum SNDR of 55.4dB and a maximum SFDR of 68.7dB at 50MS/s, respectively. The ADC with an active die area of 0.53$mm^2$ consumes 15.6mW at 50MS/s with an analog voltage of 2.0V and two digital voltages of 2.8V ($=D_H$) and 1.2V ($=D_L$).

Hybrid Scheme of Data Cache Design for Reducing Energy Consumption in High Performance Embedded Processor (고성능 내장형 프로세서의 에너지 소비 감소를 위한 데이타 캐쉬 통합 설계 방법)

  • Shim, Sung-Hoon;Kim, Cheol-Hong;Jhang, Seong-Tae;Jhon, Chu-Shik
    • Journal of KIISE:Computer Systems and Theory
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    • v.33 no.3
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    • pp.166-177
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    • 2006
  • The cache size tends to grow in the embedded processor as technology scales to smaller transistors and lower supply voltages. However, larger cache size demands more energy. Accordingly, the ratio of the cache energy consumption to the total processor energy is growing. Many cache energy schemes have been proposed for reducing the cache energy consumption. However, these previous schemes are concerned with one side for reducing the cache energy consumption, dynamic cache energy only, or static cache energy only. In this paper, we propose a hybrid scheme for reducing dynamic and static cache energy, simultaneously. for this hybrid scheme, we adopt two existing techniques to reduce static cache energy consumption, drowsy cache technique, and to reduce dynamic cache energy consumption, way-prediction technique. Additionally, we propose a early wake-up technique based on program counter to reduce penalty caused by applying drowsy cache technique. We focus on level 1 data cache. The hybrid scheme can reduce static and dynamic cache energy consumption simultaneously, furthermore our early wake-up scheme can reduce extra program execution cycles caused by applying the hybrid scheme.