• Journal of KIISE:Computer Systems and Theory
• /
• v.27 no.7
• /
• pp.684-694
• /
• 2000

For designing circuits for low power systems, the capacitance is an important factor for the power dissipation. Since the capacitance of a gate is proportional to the area of the gate, we can reduce the total power consumption of a circuit by reducing the total area of gates, where total area is a simple sum of all gate areas in the circuit. To reduce the total area, transistor resizing can be used. While resizing transistors, inserting buffer in the proper position can help reduce the total area. In this paper we propose two methods for concurrent transistor sizing and buffer insertion. One method uses template window simulation and the other uses extrapolation. Experimental results show that concurrent transistor sizing with buffer insertion achieved 10-20% more reduction of the total area than when it was done without buffer insertion and template window simulation is more efficient than extrapolation.

• Journal of Sensor Science and Technology
• /
• v.27 no.3
• /
• pp.182-185
• /
• 2018

Zinc oxide (ZnO) thin films have the advantages of growing at a low temperature and obtaining high charge mobility (carrier mobility) [1]. Furthermore, the zinc oxide thin film can be used to control application resistance depending on its oxygen content. ZnO has the desired physical properties, a transparent nature, with a flexible display that makes it ideal for use as a thin-film transistor. Though these transparent flexible thin-film transistors can be manufactured in various manners, manufacturing large-area transistors using a solution process is easier owing to the low cost and flexible substrate. The advantage of being able to process at low temperatures has been attracting attention as a preferred method. However, in the case of a thin-film transistor fabricated through a solution process, it is reported that charge mobility is lower. To improve upon this, a method of improving the crystallinity through heat treatment and increasing electron mobility has been reported. However, as the heat treatment temperature is relatively high at $500^{\circ}C$, an application where a flexible substrate is absent would be more suitable.

• Polymer(Korea)
• /
• v.30 no.3
• /
• pp.253-258
• /
• 2006

We have fabricated vortical type organic thin film transistors (OTFTs) consisting of ITO/n type active material/Al gate/n type active material/Al using F16CuPc, NTCDA, PTCDA and PTCDI C-8. The effect of mobility of n type active materials and thin film thickness on current-voltage (I-V) characteristics and on/off ratios were investigated. The vortical type organic transistor using PTCDI C-8 exhibited low operation voltage and high on-off ratio. In addition, we have investigated the feasibility of application in organic light emitting transistor using light emitting polymer. Especially, the light emitting transistor consisting of ITO/PEDOT-PSS/P3HT/F16CuPc/Al gate/F16CuPc/Al showed the maximum quantum efficiency of 0.054.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.16 no.5
• /
• pp.657-663
• /
• 2016

In this work, a novel silicon (Si) based floating body synaptic transistor (SFST) is studied to mimic the transition from short-term memory to long-term one in the biological system. The structure of the proposed SFST is based on an n-type metal-oxide-semiconductor field-effect transistor (MOSFET) with floating body and charge storage layer which provide the functions of short- and long-term memories, respectively. It has very similar characteristics with those of the biological memory system in the sense that the transition between short- and long-term memories is performed by the repetitive learning. Spike timing-dependent plasticity (STDP) characteristics are closely investigated for the SFST device. It has been found from the simulation results that the connectivity between pre- and post-synaptic neurons has strong dependence on the relative spike timing among electrical signals. In addition, the neuromorphic system having direct connection between the SFST devices and neuron circuits are designed.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.11
• /
• pp.35-42
• /
• 2004

A CMOS folding ADC with transistor differential pair folding circuit for low power consumption and high speed operation is presented in this paper. This paper explains the theory of transistor differential pair folding technique and many advantages compared with conventional folding and interpolation circuits. A ADC based on transistor differential pair folding circuit uses 16 fine comparators and 32 interpolation resistors. So it is possible to achieve low power consumption, high speed operation and small chip size. Design technology is based on fully standard 0.25${\mu}{\textrm}{m}$ double poly 2 metal n-well CMOS process. A power consumption is 45mW at 2.5V applied voltage and 250MHz sampling frequency. The INL and DNL are within $\pm$0.15LSB and $\pm$0.15LSB respectively. The SNDR is approximately 50dB at 10MHz input frequency.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2004.05a
• /
• pp.177-180
• /
• 2004

In this study, we report a novel encapsulation method for longevity of an organic thin-film transistor (OTFT) using pentaceneby means of an adhesive multiplayerincluded Al film. For encapsulation of OTFTs, the Al film adhered onto the OTFT in a dry nitrogen atmosphere using a proper adhesive. A lifetime, which was defined as the time necessary to reduce mobility to 2% of initial mobility value, was observed from the typical $I_{D-VD}$ characteristics of the field-effect transistor (FET). The initial field effect mobility ${\mu}$ was measured to be $2.0{\times}10^{-1}\;cm^2/Vs$. The characterization was maintained for long times in air. No substantial degeneration occurred. The performance and the stability are probably due to the encapsulation effect.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.8 no.2
• /
• pp.24-33
• /
• 1971

A noble method of delta modulation by means of pair transistor circuit having negative resistance charcteristic is presented. An RC parallel circuit is inserted between two eiuitter tarminals of the pair transistor circuit, and their emitters are driven by a square pulsed current source. Basically this is a relaxation oscillator circuit. But when the value of capacitors and resistanc R, and the pulse height of driving source are properly chosen, the RC parallel circuit apparently functions as integrating circuit of driviving pulses. Compared with the integrated voltage of capacitor C, a signal input voltatage supplied in series with RC parallel circuit between two emitters makes on or off either of the pair transistors. as the result, one bit pulse is sent out from the coupling resistance terminal of conducted transistor. The circuit diagram used for this experiment is presented, it i% composed with simple mod ulster circuit, differential amplifier and pulse shaping amplifier, The characteristics of the components of this ciruit are discussed, and especially quantumized noise in this delta modulation system is discussed in order to improve the signal to noise ratio which has a close relation with circut constants, quantumized voltage, pulse height and width of driving current source.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.6 no.1
• /
• pp.22-29
• /
• 2006

We demonstrate highly manufacturable Multi-channel Field Effect Transistor (McFET) on bulk Si wafer. McFET shows excellent transistor characteristics, such as $5{\sim}6 times higher drive current than planar MOSFET, ideal subthreshold swing, low drain induced barrier lowering (DIBL) without pocket implantation and negligible body bias dependency, maintaining the same source/drain resistance as that of a planar transistor due to the unique feature of McFET. And suitable threshold voltage ($V_T$) for SRAM operation and high static noise margin (SNM) are achieved by using TiN metal gate electrode.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.25 no.1
• /
• pp.24-28
• /
• 2012

In this study, we fabricated an amorphous InGaZnO pseudo-MOS transistor (a-IGZO ${\Psi}$-MOSFET) with a stacked $Si_3N_4/SiO_2$ (NO) gate dielectric and evaluated reliability of the devices with various thicknesses of a $SiO_2$ buffer layer. The roles of a $SiO_2$ buffer layer are improving the interface states and preventing degradation caused by the injection of photo-created holes because of a small valance band offset of amorphous IGZO and $Si_3N_4$. Meanwhile, excellent electrical properties were obtained for a device with 10-nm-thick $SiO_2$ buffer layer of a NO stacked dielectric. The threshold voltage shift of a device, however, was drastically increased because of its thin $SiO_2$ buffer layer which highlighted bias and light-induced hole trapping into the $Si_3N_4$ layer. As a results, the pseudo-MOS transistor with a 20-nm-thick $SiO_2$ buffer layer exhibited improved electrical characteristics and device reliability; field effective mobility(${\mu}_{FE}$) of 12.3 $cm^2/V{\cdot}s$, subthreshold slope (SS) of 148 mV/dec, trap density ($N_t$) of $4.52{\times}1011\;cm^{-2}$, negative bias illumination stress (NBIS) ${\Delta}V_{th}$ of 1.23 V, and negative bias temperature illumination stress (NBTIS) ${\Delta}V_{th}$ of 2.06 V.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2011.02a
• /
• pp.118-118
• /
• 2011

The Nano-Floating Gate Memory(NFGM) devices with ZnO:Cu thin film embedded in Al2O3 and AlOx-SAOL were fabricated and the electrical characteristics were evaluated. To further improve the scaling and to increase the program/erase speed, the high-k dielectric with a large barrier height such as Al2O3 can also act alternatively as a blocking layer for high-speed flash memory device application. The Al2O3 layer and AlOx-SAOL were deposited by MLD system and ZnO:Cu films were deposited by ALD system. The tunneling layer which is consisted of AlOx-SAOL were sequentially deposited at $100^{\circ}C$. The floating gate is consisted of ZnO films, which are doped with copper. The floating gate of ZnO:Cu films was used for charge trap. The same as tunneling layer, floating gate were sequentially deposited at $100^{\circ}C$. By using ALD process, we could control the proportion of Cu doping in charge trap layer and observe the memory characteristic of Cu doping ratio. Also, we could control and observe the memory property which is followed by tunneling layer thickness. The thickness of ZnO:Cu films was measured by Transmission Electron Microscopy. XPS analysis was performed to determine the composition of the ZnO:Cu film deposited by ALD process. A significant threshold voltage shift of fabricated floating gate memory devices was obtained due to the charging effects of ZnO:Cu films and the memory windows was about 13V. The feasibility of ZnO:Cu films deposited between Al2O3 and AlOx-SAOL for NFGM device application was also showed. We applied our ZnO:Cu memory to thin film transistor and evaluate the electrical property. The structure of our memory thin film transistor is consisted of all organic-inorganic hybrid structure. Then, we expect that our film could be applied to high-performance flexible device.----못찾겠음......