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A Design of 250-MSamples/s 8-Bit Folding Analog to Digital Converter using Transistor Differential Pair Folding Technique  

이돈섭 (두원공과대학 소프트웨어개발과)
곽계달 (한양대학교 전자전기컴퓨터공학부)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.41, no.11, 2004 , pp. 35-42 More about this Journal
Abstract
A CMOS folding ADC with transistor differential pair folding circuit for low power consumption and high speed operation is presented in this paper. This paper explains the theory of transistor differential pair folding technique and many advantages compared with conventional folding and interpolation circuits. A ADC based on transistor differential pair folding circuit uses 16 fine comparators and 32 interpolation resistors. So it is possible to achieve low power consumption, high speed operation and small chip size. Design technology is based on fully standard 0.25${\mu}{\textrm}{m}$ double poly 2 metal n-well CMOS process. A power consumption is 45mW at 2.5V applied voltage and 250MHz sampling frequency. The INL and DNL are within $\pm$0.15LSB and $\pm$0.15LSB respectively. The SNDR is approximately 50dB at 10MHz input frequency.
Keywords
ADC; AD converter;
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