• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1771-1773
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• 2007

Surface modification of the gate dielectric has a strong influence on the performance of printed transistors. The surface modification occurs between the gate dielectric and semiconductor. The printed transistor with evaporated vanadium pentoxide ($V_2O_5$) modification exhibits a mobility of $0.2cm^2\;V^{-1}\;s{-1}$ and a subthreshold slope of 1.47 V/decade.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1308-1311
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• 2007

Leakage current produced by backside illumination on bottom-gated amorphous silicon thin film transistor has been investigated. The experimental results show that the leakage current of bottomgated structure is significantly dependent on the shape of amorphous silicon pattern. A proper design of amorphous silicon pattern has been suggested in viewpoint of reducing the leakage current as well as mass production.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.855-858
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• 2001

The stress induced leakage currents of thin silicon oxides is investigated in the VLSI implementation of a self learning neural network integrated circuits using a linearity synapse transistor. The channel current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between 41 ${\AA}$, 86${\AA}$, which have the channel width ${\times}$ length 10 ${\times}$1${\mu}$m, 10 ${\times}$0.3${\mu}$m respectively. The stress induced leakage currents will affect data retention in synapse transistors and the stress current, transient current is used to estimate to fundamental limitations on oxide thicknesses. The synapse transistor made by thin silicon oxides has represented the neural states and the manipulation which gaves unipolar weights. The weight value of synapse transistor was caused by the bias conditions. Excitatory state and inhitory state according to weighted values affected the channel current. The stress induced leakage currents affected excitatory state and inhitory state.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.97-98
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• 2006

For high performance transistor in the 0.14um generation, high speed sram is using a weak region of SCE(Short Channel Effect). It causes serious SCE problem (Vth Roll-Off and Punch-Through etc). This paper shows improvement of Vth roll-off and Ion/Ioff characteristics through high concentration Pocket implant, LDD(Light Dopped Dram) and low energy Implant to reduce S/D Extension resistance. We achieve stabilized Vth and Improved transistor Ion/Ioff performance of 10%.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.1
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• pp.23-28
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• 2008

In this paper, transient characteristics of the Punch Through Insulated Gate Bipolar Transistor (PT-IGBT) have been studied. On the contrary to Non-Punch Through Insulated Gate Bipolar Transistor(NPT-IGBT), it has a buffer layer and reduces switching power loss. It has a simple drive circuit controlled by the gate voltage of the MOSFET and low on-state resistance of the bipolar junction transistor. The transient characteristics of the PT-IGBT have been analyzed analytically. Excess minority carrier and charge distribution in active base region, the rate of anode voltage with time are expressed analytically by adding the influence of buffer layer. The experimental data is obtained from manufacturer. The theoretical predictions of the analysis have been compared with the experimental data obtained from the measurement of a device(600 V, 15 A) and show good agreement.

• ETRI Journal
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• v.25 no.5
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• pp.288-296
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• 2003

In this study, we present a 260k color TFT LCD driver chip set that consumes only 5 mW in the module, which has exceptionally low power consumption. To reduce power consumption, we used many power-lowering schemes in the logic and analog design. A driver IC for LCDs has a built-in graphic SRAM. Besides write and read operations, the graphic SRAM has a scan operation that is similar to the read operation of one row-line, which is displayed on one line in an LCD panel. Currently, the embedded graphic memory is implemented by an 8-transistor leaf cell and a 6-transistor leaf cell. We propose an efficient scan method for a 6-transistor embedded graphic memory that is greatly improved over previous methods. The proposed method is implemented in a 0.22 ${\mu}m$ process. We demonstrate the efficacy of the proposed method by measuring and comparing the current consumption of chips with and without our proposed scheme.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.2
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• pp.63-75
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• 1993

As the CMOS technology becomes the most dominant circuit realization method, the cost problem for the test which includes both the transistor-level FET stuck-on and stuck-off faults and the gatelevel stuck-at faults becomes more and more serious. In accordance, this paper proposes a test set and its generation algorithm, which handles both the transistor-level faults and the gate-level faults, thus can unify the test steps during the IC design and fabrication procedure. This algorithm uses only the logic equation of the given logic function as the input resource without referring the transistor of gate circuit. Also, the resultant test set from this algorithm can improve in both the complexity of the generation algorithm and the time to apply the test as well as unify the test steps in comparing the existing methods.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.75-87
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• 2012

A design paradigm using sequential geometric programming is presented to accurately design CMOS op amps with BSIM3. It is based on new adaptive modeling of transistor parameters through the operating point simulation. This has low modeling cost as well as great simplicity and high accuracy. The short-channel dc, high-frequency small-signal, and short-channel noise models are used to characterize the physical behavior of submicron devices. For low-power and low-voltage design, this paradigm is extended to op amps operating in the subthreshold region. Since the biasing and modeling errors are less than 0.25%, the characteristics of the op amps well match simulation results. In addition, small dependency of design results on initial values indicates that a designed op amp may be close to the global optimum. Finally, the design paradigm is illustrated by optimizing CMOS op amps with accurate transfer function.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.635-640
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• 2016

Tunnel field-effect transistor (TFET) is a promising candidate for the next-generation electron device. However, technical issues remain for their practical application: poor current drivability, shor-tchannel effect and ambipolar behavior. We propose herein a novel recessed-channel TFET (RTFET) with the asymmetric source and drain. The specific design parameters are determined by technology computer-aided design (TCAD) simulation for high on-current and low S. The designed RTFET provides ${\sim}446{\times}$ higher on-current than a conventional planar TFET. And, its average value of the S is 63 mV/dec.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.258-260
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• 2008

Developed halftone exposure technique was successfully applied to the fabrication of narrow transistor channels below $4\;{\mu}m$ with conventional photolithography method. Asymmetric slits concept of photo mask was applied to make channel lengths (L) shorter for thin film transistor's (TFT) high performance. These short channel TFTs verified better quality transistor characteristics.