• Journal of Electrical Engineering and Technology
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• 제11권6호
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• pp.1763-1768
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• 2016

This paper presents the electrical characteristics of the gallium nitride (GaN) current aperture vertical electron transistor (CAVET) by using two-dimensional (2-D) technology computer-aided design (TCAD) simulations. The CAVETs are considered as the alternative device due to their high breakdown voltage and high integration density in the high-power applications. The optimized design for the CAVET focused on the electrical performances according to the different gate-source length ($L_{GS}$) and aperture length ($L_{AP}$). We analyze DC and RF parameters inducing on-state current ($I_{on}$), threshold voltage ($V_t$), breakdown voltage ($V_B$), transconductance ($g_m$), gate capacitance ($C_{gg}$), cut-off frequency ($f_T$), and maximum oscillation frequency ($f_{max}$).

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.3-4
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• 2009

As device process technology advances, effective channel length, the thickness of gate oxide, and supply voltage decreases. This paper describes a novel electrostatic discharge (ESD) protection device which has current feedback for high ESD immunity. A conventional Gate-Grounded NMOS (GGNMOS) transistor has only one ESD current path, which makes, the core circuit be in the safe region, so an GGNMOS transistor has low current immunity compared with our device which has current feedback path. To simulate our device, we use conventional $0.18\;{\mu}m$ technology parameters with a gate oxide thickness of $43\;{\AA}$ and power supply voltage of 1.8 V. Our simulation results indicate that the area of our ESD protection, device can be smaller than a GGNMOS transistor, and ESD immunity is better than a GGNMOS transistor.

• 대한전자공학회논문지
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• 제8권3호
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• pp.15-26
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• 1971

본논문은 트란지스터발진기의 발진영역과 부저항의 변화에 대하여 하나의 새로운 방법을 써서 고찰한 것이다. 트란지스터귀환발진기의 발진영역을, 귀환소자임피이던스의 복소평면상에 나타내면 원이 된다. 그리고, 귀환소자임퍼이던스의 저항분을 일정하게 하고, 리액턴스분을 변화시키거나, 혹은 이와 반대로 리액틴스분을 일정하게하고, 저항분을 변화시킬 때, 출력콘덕턴스가 극소로 되는 점의 궤적은 쌍곡선이 된다. 트란지스터수정발진기에서는, 발진영역은 부하임퍼이던스의 복소평면상에서, 입력임피이던스의 실수부 및 허수부를 0이 되게 하는, 두개의 원에 의하여 정해진다. 그리고, 부하임피이던스의 저항분을 일정하게 하고 리액턴스분을 변화시키거나, 혹은 반대로 리액턴스분을 일정하게 하고 저항분을 변화시킬 때, 입력저항을 극대 또는 극소로 되게 한는 점의 궤적은, 네 개의 직선이 된다.

• 한국정보통신학회논문지
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• 제16권12호
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• pp.2741-2746
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• 2012

본 연구에서는 기존의 질화알루미늄갈륨/질화갈륨 이종접합 구조에서 강한 분극현상으로 인하여 구현하기 어려웠던 상시불통형 소자를 질화알루미늄갈륨 기판 혹은 버퍼층을 이용하여 구현하는 방법을 제안한다. 질화알루미늄갈륨 기판 혹은 버퍼층 위에 더 높은 Al 몰분율을 갖는 장벽층을 성장하고 최상부에 질화갈륨 층을 추가 성장하여 분극전하를 상쇄시키는 방법을 이용하여 선택적으로 게이트 아래의 채널만 공핍시켜 상시불통형 소자를 구현할 수 있다. 이를 통하여 본 연구에서는 상용 전력소자에서 요구하는 게이트 문턱전압 2 V 이상을 갖는 질화알루미늄갈륨 이종접합 전계효과 트랜지스터 에피구조를 제안한다.

• 대한전자공학회논문지SD
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• 제37권11호
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• pp.1-8
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• 2000

본 논문에서는 인터커넥트 라인을 구동하는 CMOS소자의 게이트 폭의 변화에 따라 소자 및 인터커넥트라인에 의한 RC 지연시간이 어떤 특성을 보이는지에 대하여 분석하였다. 인터커넥트 라인의 캐패시턴스 성분만이 주로 나타나는 구조에서는 MOSFET의 크기가 커질수록 전체 지연시간이 감소하는 특성을 보였다. 반면에 인터커넥트 라인의 저항 및 캐패시턴스 성분이 대등하게 지연시간에 영향을 미치는 구조에서는 전체회로의 지연시간이 최소가 되는 MOSFET 크기가 존재함을 수식적으로 제안하고 실험치와 비교하여 잘맞음을 증명하였다.

• 대한전자공학회논문지SD
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• 제40권4호
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• pp.13-20
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• 2003

반도체 소자이론에 근거한 집적회로용 BJT의 역포화 전류 모델을 제시한다. 공정 조건으로부터 베이스 영역의 불순물 분포를 구하는 방법과 원형 에미터 구조를 갖는 Lateral PNP BJT와 Vertical NPN BJT의 베이스 Gummel Number를 정교하게 계산하는 방법을 제시한다. 제안된 방법의 타당성을 검증하기 위해 20V와 30V 공정을 기반으로 제작한 NPN BJT와 PNP BJT의 역포화 전류를 실측치와 비교한 결과, NPN BJT는 6.7%의 평균상대오차를 보이고 있으며 PNP BJT는 6.0%의 평균 상태오차를 보인다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권1호
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• pp.41-44
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• 2004

The trend of decreasing the minimal structure sizes in microelectronics is still being continued. Therefore in its roadmap the Semiconductor Industries Association predicts a printed minimum MOS-transistor channel length of 10 nm for the year 2018. Although the resolution of optical lithography still dramatically increases, there are known and proved solutions for structure sizes significantly below 50 nm up to now. In this work a new method for the fabrication of extremely small MOS-transistors with a channel length and width below 50 nm with low demands to the used lithography will be explained. It's a further development of our deposition and etchback technique which was used in earlier research to produce transistors with very small channel lengths down to 30 nm, with a scaling of the transistor's width. The used technique is proved in a first charge of MOS-transistors with a channel area of W=200 nm and L=80 nm. The full CMOS compatible technique is easily transferable to almost any other technology line and results in an excellent homogeneity and reproducibility of the generated structure size. The electrical characteristics of such small transistor will be analyzed and the ultimate limits of the technique will be discussed.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.375-375
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• 2014

Layered semiconductor materials can be a promising candidate for large-area thin film transistors (TFTs) due to their relatively high mobility, low-power switching, mechanically flexibility, optically transparency, and amenability to a low-cost, large-area growth technique like thermal chemical vapor deposition (CVD). Unlike 2D graphene, series of transition metal dichalcogenides (TMDCs), $MX_2$ (M=Ta, Mo, W, X=S, Se, Te), have a finite bandgap (1~2 eV), which makes them highly attractive for electronics switching devices. Recently, 2D $MoS_2$ materials can be expected as next generation high-mobility thin-film transistors for OLED and LCD backplane. In this paper, we investigate in detail the electrical characteristics of 2D layered $MoS_2$ local bottom-gated transistor with the same device structure of the conventional thin film transistor, and expect the feasibility of display application.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제55권3호
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• pp.111-115
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• 2006

We investigated accelerated soft error rate(ASER) in 8M static random access memory(SRAM) cells. The effects on ASER by well structure, operational voltage, and cell transistor threshold voltage are examined. The ASER decreased exponentially with respect to operational voltage. The chips with buried nwell1 layer showed lower ASER than those either with normal well structure or with buried nwell1 + buried pwell structure. The ASER decreased as the ion implantation energy onto buried nwell1 changed from 1.5 MeV to 1.0 MeV. The lower viscosity of the capping layer also revealed lower ASER value. The decrease in the threshold voltage of driver or load transistor in SRAM cells caused the increase in the transistor on-current, resulting in lower ASER value. We confirmed that in order to obtain low ASER SRAM cells, it is necessary to also the buried nwell1 structure scheme and to fabricate the cell transistors with low threshold voltage and high on-current.

• International Journal of Precision Engineering and Manufacturing
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• 제9권4호
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• pp.3-10
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• 2008

Micro-electrical discharge machining (micro-EDM) is an effective method for machining all types of conductive materials regardless of hardness. Since micro-EDM is an electro-thermal process, the energy supplied by the pulse generator is an important factor in determining the effectiveness of the process. In this study, an investigation was conducted on the micro-EDM of tungsten carbide (WC) to compare the performance of transistor and resistance/capacitance (RC) pulse generators in obtaining the best quality micro-hole. The performance was measured by the machining time, material removal rate, relative tool wear ratio, surface quality, and dimensional accuracy. The RC generator was more suited for minimizing the pulse energy, which is a requirement for fabricating micro-parts. The smaller-sized debris formed by the low-discharge energy of RC micro-EDM could be easily flushed away from the machined zone, resulting in a surface free of burrs and resolidified molten metal. The RC generator also required much less time to obtain the same quality micro-hole in WC. Therefore, RC generators are better suited for fabricating micro-structures, producing good surface quality and better dimensional accuracy than the transistor generators, despite their higher relative tool wear ratio.